TMS320F28377S: Code placed at end of flash bank 0 causes NMI interrupt (in 0x000B FFF0 - 0x000B FFFF range)

Hi Mads Lind,

Thank you for bringing this to our attention.

Gel file disables ECC.  Did you notice an ECC error and/or ITRAP when this failure occurs?  Also, please check the values of RESC, NMIFLG and flash ECC registers (UNC_ERR_ADDR_LOW and UNC_ERR_ADDR_HIGH in TRM).

I will check with the advisory author to confirm whether the advisory is applicable for the end of bank0 or not (even though there is another bank immediately, the flash wrapper is different - I will ask in this context).  Hope you configured the wait-states correctly for both banks.

Thanks and regards,

Vamsi

Hi Vamsi

Many thanks for the quick response.

I just checked the registers you suggested.

NMIFLG = 0x0009:   NMIINT and FLUNCERR (Flash Uncorrectable Error NMI Flag)

RESC = 0xC0000000: TRSTn_pin_status and XRSn_pin_status are 1, I believe this is normal, normal power on.

Flash0EccRegs:
UNC_ERR_ADDR_LOW = 0x000C0000
UNC_ERR_ADDR_LOW = 0

Flash1EccRegs:
UNC_ERR_ADDR_LOW = 0
UNC_ERR_ADDR_LOW = 0

So does it look like the Flash bank 0 causes fault at the start address of Flash Bank 1? 
Maybe because as you say the flash wrapper is different?

Both flash banks are configured correctly.

Mads Lind,

Thank you for checking those registers.

Instead of executing the application, can you load simple code in to RAM to read the entire flash (both banks) with ECC enabled?  Pleae don't erase the application in flash - Keep it as is and just check if ECC errors show up for reads.

This helps to debug this further.

Thanks and regards,
Vamsi

Hi Vamsi

I added a function in ram to the application, so not a separate application. Hope this is good enough.

I executed it after running InitSysCtrl etc. so that the ramfuncs has been copied from flash to ram.

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #pragma CODE_SECTION(".TI.ramfunc");
    #else
        #pragma CODE_SECTION("ramfuncs");
    #endif
#endif
void flashReadTest()
{
    volatile uint16_t *flash_start = (uint16_t *) 0x00080000;
    volatile uint16_t *flash_end   = (uint16_t *) 0x00100000;

    uint32_t sum = 0;

//    ESTOP0;

    while (flash_start != flash_end)
    {
        sum += *flash_start++;
    }

//    ESTOP0;
}

The function executed without any problems.

Hi Vamsi

Yes, ECC is enabled for both flash banks.
So the conclusion could be that DATA read is OK for the entire flash area, but program execution is not for end of flash bank 0.

I have now taken measures to avoid the area in our linker file.

Many thanks for quick support :-)

Mads Lind,

Thank you for the confirmation.

I will update here once I get more details from our design team.  I am closing this post for now.

Clarification: 

For fetches: When prefetch is enabled, FMC0 fetches beyond bank0 space in to bank1 - which is not accessible for FMC0 and hence fails.

Data reads: Data cache fills does not go beyond the current 128-bit flash word (aligned on 128-bit boundary).  Hence, data errors should not cause an issue.  

Above is what I wanted to confirm from your experiment - to establish that this issue is due to prefetch beyond Bank0 by FMC0 and not from a real ECC error (ECC error that you got is not an actual ECC error - it is due to prefetch giving incorrect opcode).

Best regards,

Vamsi

Mads Lind,

Do you have any further questions on this?  Or Can I close this post?  Please let me know.

Thanks and regards,
Vamsi