Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
Hi, I'm trying to debug a difficult issue and wondering if anyone here has any insights into it. My firmware application runs out of flash. I had a bug in my linker file where the .pinit section was mapped to ram instead of flash. The result of this was that my code would run fine when I programmed/debugged the code, but when I power cycled the board and booted from flash all of my global objects (c++ classes) were not initialized correctly.
After fixing this bug to have .pinit map to flash instead of ram, my program still runs correctly when I load it from the debugger, but when I power cycle the board and boot from flash nothing happens, as in, not even the first few lines of main seem to execute, judging based on an LED toggle. I then commented out several of the global objects, and when I only have a few defined the program runs, but when I pass a certain threshold of global objects, it doesn't matter which objects in particular, nothing runs and the cpu seemingly gets locked before reaching the first few lines of main.
I'll attach my cmd file here. Any suggestions on how to debug this further would be appreciated.
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C
MEMORY
{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B0, length = 0x000250
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
// RAMD0 : origin = 0x00C000, length = 0x000800
// RAMD1 : origin = 0x00C800, length = 0x000800
RAMD0_1 : origin = 0x00C000, length = 0x001000
// RAMLS0 : origin = 0x008000, length = 0x001000
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00D000, length = 0x005000
// RAMGS0 : origin = 0x00D000, length = 0x001000
// RAMGS1 : origin = 0x00E000, length = 0x001000
// RAMGS2 : origin = 0x00F000, length = 0x001000
// RAMGS3 : origin = 0x010000, length = 0x001000
// RAMGS_4 : origin = 0x011000, length = 0x004000
// RAMGS4 : origin = 0x011000, length = 0x001000
RAMGS5 : origin = 0x012000, length = 0x004000
// RAMGS5 : origin = 0x012000, length = 0x001000
// RAMGS6 : origin = 0x013000, length = 0x001000
// RAMGS7 : origin = 0x014000, length = 0x001000
// RAMGS8 : origin = 0x015000, length = 0x001000
RAMGS9 : origin = 0x016000, length = 0x001000
RAMGS10 : origin = 0x017000, length = 0x005000
// RAMGS10 : origin = 0x017000, length = 0x001000
// RAMGS11 : origin = 0x018000, length = 0x001000
// RAMGS12 : origin = 0x019000, length = 0x001000
// RAMGS13 : origin = 0x01A000, length = 0x001000
// RAMGS14 : origin = 0x01B000, length = 0x001000
RAMGS15 : origin = 0x01C000, length = 0x001000
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN, ALIGN(4)
.text : >> FLASHB | FLASHH | FLASHI | FLASHJ | FLASHK | FLASHL | FLASHM | FLASHN, ALIGN(4)
.cinit : > FLASHG, ALIGN(4)
.switch : > FLASHG, ALIGN(4)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1
DMARAML4 : > RAMGS0
#if defined(__TI_EABI__)
.init_array : > FLASHG, ALIGN(8)
.bss : > RAMGS0 , ALIGN(4)
.bss:output : > RAMLS0, ALIGN(4)
.bss:cio : > RAMLS0
.data : > RAMLS0
.sysmem : > RAMLS0
/* Initalized sections go in Flash */
.const : > FLASHG, ALIGN(8)
#else
.pinit : > FLASHG , ALIGN(8)
.ebss : > RAMGS0
.esysmem : > RAMGS10 , ALIGN(8)
.cio : > RAMLS6 | RAMLS7 , ALIGN(8)
/* Initalized sections go in Flash */
.econst : > FLASHG, ALIGN(8)
#endif
/* Flash Programming Buffer */
BufferDataSection : > RAMLS5, ALIGN(8)
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
/* CLA specific sections */
#if defined(__TI_EABI__)
Cla1Prog : LOAD = FLASHF,
RUN = RAMLS4 | RAMLS5,
LOAD_START(Cla1funcsLoadStart),
LOAD_END(Cla1funcsLoadEnd),
RUN_START(Cla1funcsRunStart),
LOAD_SIZE(Cla1funcsLoadSize),
ALIGN(8)
#else
Cla1Prog : LOAD = FLASHF,
RUN = RAMLS4 | RAMLS5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
ALIGN(8)
#endif
ClaData : > RAMLS3
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
GROUP { .TI.ramfunc { -l F021_API_F2837xD_FPU32.lib} }
LOAD = FLASHD,
RUN = RAMD0_1 | RAMGS5,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
GROUP { .TI.ramfunc { -l F021_API_F2837xD_FPU32.lib} }
LOAD = FLASHD,
RUN = RAMD0_1 | RAMGS5,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
GROUP { ramfuncs { -l F021_API_F2837xD_FPU32.lib} }
LOAD = FLASHD,
// RUN = RAMLS0,
RUN = RAMD0_1,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#endif
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, type=NOINIT
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, type=NOINIT
/* SFRA specific sections */
SFRA_F32_Data : > RAMGS9, ALIGN = 64
#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS2
.scratchpad : > RAMLS2
.bss_cla : > RAMLS2
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASHF,
RUN = RAMLS6,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
ALIGN(8)
#else
.const_cla : LOAD = FLASHF,
RUN = RAMLS6,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
ALIGN(8)
#endif
#endif //CLA_C
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
}
