TMS320F28388D: EMIF CS timing question

Emma Wang

Expert 5420 points

Part Number: TMS320F28388D

Hi expert,

I am supporting customer using EMIF communicating FPGA.

but the CS cycle is too long and customer need to speed up.

customer configuration code is as below:

Emif1Regs.ASYNC_CS2_CR.bit.SS =1 
Emif1Regs.ASYNC_CS2_CR.bit.EW =0
Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP =0
Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE =0
Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD =0
Emif1Regs.ASYNC_CS2_CR.bit.R_TA =0 
Emif1Regs.ASYNC_CS2_CR.bit.ASIZE =1

they set setup, hold, strobe all to zero for test. but the question is the high level time is too long ,about 40ns. and they hope to shrink it.

In the runtime code, they use a read immediately following a read, so I suppoes it is the delay between two reads.

do you have any ideas on shrinking the delay and shortening the high level voltage time?

Emma

over 5 years ago

0 Vivek Singh over 5 years ago

TI__Guru** 116971 points

Hi Emma,

What is the emif clock frq set in this case? It look like 100MHz which means CS is high for 4 cycle which looks ok because 1 cycle for setup and one cycle for strobe is used and one cycle for next access. One extra cycle could be coming due to C code (you can check the assembly).

Regards,

Vivek Singh

0 Emma Wang over 5 years ago in reply to Vivek Singh

TI__Expert 5420 points

Vivek,

Yes, the EMIF frequency is 100MHz, But it shows by Figure 5-18. EMxWAIT Read Timing Requirements in datasheet. the setup, strobe and hold are all happen on low voltage level time. so it can not do these three things.

and We have customer use DMA to test, it will save about 5ns in the high voltage level time.

in real case, it should be longer for low voltage time, so they want to shorten high voltage level time.

Emma

0 Vivek Singh over 5 years ago in reply to Emma Wang

TI__Guru** 116971 points

Why not change the EMIF frq to 200MHz so that all the timings are multiple of 5ns instead of 10ns ? If they want to increase the low time then they have to increase the STROBE timing.

Regards,

Vivek Singh

0 Vivek Singh over 5 years ago in reply to Vivek Singh

TI__Guru** 116971 points

Hi Emma,

Let us know if you have any further queries on this topic.

Regards,

Vivek Singh

0 Emma Wang over 5 years ago in reply to Vivek Singh

TI__Expert 5420 points

Hi Vivek,

Customer have tested 200M.

But they hope to short the high level voltage time.

As my first post talks about: they set setup, hold, strobe all to zero for test. but the question is the high level time is too long ,about 40ns. and they hope to shrink it.

or could you kindly give the explainations on the reason causing the high level time about 40ns?

Emma

0 Vivek Singh over 5 years ago in reply to Emma Wang

TI__Guru** 116971 points

Emma,

I mentioned in my Ist post the calculation. 0 configuration means 1 cycle and not 0 cycle.

Regards,

Vivek Singh

0 Emma Wang over 5 years ago in reply to Vivek Singh

TI__Expert 5420 points

Vivek,

yes, but I am mentioning the high level time, setup, hold, strobe procesure are all happens in low level time on CS signal.

Emma

0 Vivek Singh over 5 years ago in reply to Emma Wang

TI__Guru** 116971 points

Emma,

Ok, I see. Customer is using STROBE SELECT mode in this case where CS is driven low even during SETUP and HOLD period so yes in that case CS should not be high for that long unless it is because of back to back access code. Can you ask customer to do a 32bit access instead of 16bit back-to-back access and see how the waveform look in that case ?

Regards,

Vivek Singh

0 Vivek Singh over 5 years ago in reply to Vivek Singh

TI__Guru** 116971 points

Hi Emma,

Did customer tried 32bit access and see any difference in waveform ?

Regards,

Vivek Singh

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TMS320F28388D: EMIF CS timing question