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TMS320F28388D: M4 ram read from CPUTOM4_MSGRAM too slow

Emma Wang
Expert 5440 points

Part Number: TMS320F28388D

Hi expert,

Since CM core do not have EMIF, my customer use CPU2 to receive FPGA message and send it

To CM via IPC , but they found it is too slow for CM read RAM.

For M4 ram read from CPUTOM4_MSGRAM,

256*32 need time = 27.4us

256*16 need time = 27.4us

Read from same address or successive address needs same time.

However, customer test similarly from M4 to M4, the test result is below:

256*32 need time = 15.6us

256*16 need time = 15.6us

 

Customer wants to know why it is the difference and how to improve that?

Does uDMA a good choice? And does it make affect on CPUTOM4_MSGRAM?

BR

Emma

  • 0
    TI__Guru** 117371 points

    Hi Emma,

    CM and CPU1/CPU2 are in different clock domain (125MHz vs 200MHz) hence access to IPC rams are from M4 are synchronized  which makes it slow access. This is not the case when access to local RAM are M4 are done. This will apply to even uDMA access. 

    Regards,

    Vivek Singh