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Original question:

CCS/LAUNCHXL-F28379D: Can flash kernel example code availability

CCS/LAUNCHXL-F28379D: F2837xD_sci_flash_kernels CCS configuration

Jakub Smykla
Prodigy 230 points

Part Number: LAUNCHXL-F28379D
Other Parts Discussed in Thread: C2000WARE

Tool/software: Code Composer Studio

Going back to my previous post.

I'm trying to modify those source files to use CAN instead of SCI. 

I want to ask if they are the correct files I should be using?

C:\ti\c2000\C2000Ware_3_03_00_00\device_support\f2837xd\examples\dual\F2837xD_sci_flash_kernels\cpu01

there is also

C:\ti\c2000\C2000Ware_3_03_00_00\device_support\f2837xd\examples\dual\F2837xD_sci_flash_kernels\cpu02 

The compiler has CPU1_RAM and DUAL configuration does any one know the difference?

Since there flash is share across of the cores. What benefit can loading cpu02 kernel have?

  • 0
    TI__Mastermind 19795 points

    Hello,

    Thank you for your question! Those should be the correct file paths for this. Additionally, if you have not gotten a chance to read through this application note, this may help walk through the process needed to do what you are describing: Serial Flash Programming of C2000 Microcontrollers

    If talking about the Code Composer Studio compiler, I believe what you are discussing is the tags used to load to a single (cpu1) core or both (dual) cores of the device. Loading cpu02 kernel allows to boot CPU2 to SCI boot loader.

    Regards,

    Vince

    NOTE: Due to the national holiday this week, we may be slow to respond during this time. Thank you for your patience!

  • 0 in reply to Vince
    Prodigy 230 points

    Thanks for the input Vince.

    The flash api Kernel B has no ability to flash between Different CPUs and kernels have to be loaded individually into RAM csm unlocked and data stream flashed.

    What you have send helped. I have read one more time the TRM+overview and would be great full if you could check my understanding so far. I think what I was missing in my understanding of the processor is that the flash is totally different across the cores. 512kb of memory core 1 and 512kb core 2.

    The cpu1 has no physical access to flash of cpu2 and vice versa.

  • 0 in reply to Jakub Smykla
    Prodigy 230 points

    This is what I can see. I will try to test this somehow. RAM is shared across cores I think its possible that this could work?

  • 0 in reply to Jakub Smykla
    TI__Mastermind 19795 points

    Hello,

    For dual core IPC (inter-processor communications) see the following workshop, particularly chapter 11 (Dual-Core Inter-Processor Communications (IPC) -- Lab: Transfer data using IPC):

    https://training.ti.com/c2000-f2837xd-microcontroller-workshop

    This workshop steps through how to approach the dual-core aspect of the device.

    Regards,

    Vince