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F2812 clock pll division doesn't work

woo
Prodigy 60 points

Hi, all

 

    I am working on F2812 with CCS 3.3. My external clock input ( to pin 77, X1/XCLKIN ) is 30M, I have measured this with my oscilloscope. I want to have a CLKOUT of 150M and a period of 1s for TIMER0 to generate interrupt.

With the example project  (Example_281xCpuTimer.pjt) downloaded from TI website, I changed line  "ConfigCpuTimer(&CpuTimer0, 100, 1000000);"  into "ConfigCpuTimer(&CpuTimer0, 150, 1000000);" but the CLKOUT doesn't seem to have a 0xA/2 division, because I have a DA port to monitor the interrupt generated by TIMER0, it seems the DA output changes every 5second, which means that I am still have a 30M clock!!

I have initialized the CPU CLKOUT with "InitSysCtrl(); " in which " InitPll(0xA);" is provoked to have a 150M cpu clock.

Is there any other register that I need to set? I have read the data sheet while still don't know where did I miss. Please help to point it out. Thanks!