Part Number: TMS320F28377S
Other Parts Discussed in Thread: C2000WARE, CONTROLSUITE
We need to drive a half bridge with frequency modulation in the range of 2.5 to 4MHz. Therefore we configured the PWM channel in HR periode control. Also the deadband unit is used to generate a complementary drive signal with deadtime on PWM A and B outputs.
We recognized on Channel B a periodic jitter of 1 cklock cycle (10ns) on the falling edge.
The configuration code: (EPwm4Regs.TBPRDHR = 256)
EPwm4Regs.TBCTL.bit.FREE_SOFT = 0x02; // Free run on debugger halt
EPwm4Regs.TBCTL2.bit.SYNCOSELX = 1; // Sync Output dissable
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;
#define period 16
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
EPwm4Regs.TBPRD = period; // PWM frequency = 1/(2*TBPRD)
EPwm4Regs.CMPA.bit.CMPA = period / 2; // set duty 50% initially
EPwm4Regs.CMPA.bit.CMPAHR = (1 << 8); // initialize HRPWM extension
//EPwm4Regs.CMPB.bit.CMPB = period / 2; // set duty 50% initially
//EPwm4Regs.CMPB.all |= 1;
EPwm4Regs.TBPHS.all = 0;
EPwm4Regs.TBCTR = 0;
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down
// count mode
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
//EPwm4Regs.TBCTL.bit.PHSEN = 1;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // LOAD CMPA on CTR = 0 or CTR=per
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.AQCTLA.bit.CAD = AQ_SET; // PWM toggle high/low
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.CBU = AQ_SET; // PWM toggle high/low
EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;
EPwm4Regs.HRCNFG.bit.EDGMODEB = 3; //MEP control of both edges (TBPHSHR or TBPRDHR)
EPwm4Regs.HRCNFG.bit.EDGMODE = 3; //MEP control of both edges (TBPHSHR or TBPRDHR)
EPwm4Regs.HRCNFG.bit.AUTOCONV = 1; //Automatic HRMSTEP scaling is enabled.
EPwm4Regs.HRCNFG.all = 0x0;
EPwm4Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on
EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR
EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0
EPwm4Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on
EPwm4Regs.HRCNFG.bit.CTLMODEB = HR_CMP; // CMPBHR and TBPRDHR
EPwm4Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO_PRD; // load on CTR = 0
EPwm4Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for
//EPwm4Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
EPwm4Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution
EPwm4Regs.DBCTL.bit.HALFCYCLE = 1;
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWMxA is the source for both falling-edge and rising-edge delay.
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active high complementary (AHC). EPWMxB is inverted.
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB.
EPwm4Regs.DBCTL.bit.SHDWDBFEDMODE = 1; // Shadow mode. Operates as a double buffer. All writes via the CPU access Shadow register
EPwm4Regs.DBCTL.bit.SHDWDBREDMODE = 1; // Shadow mode. Operates as a double buffer. All writes via the CPU access Shadow register
//EPwm4Regs.DBREDHR.bit.DBREDHR = 60;
//EPwm4Regs.DBFEDHR.bit.DBFEDHR = 60;
EPwm4Regs.DBRED.bit.DBRED = 3;
EPwm4Regs.DBFED.bit.DBFED = 3;
//EPwm4Regs.HRCNFG2.bit.EDGMODEDB = DB_FULL_ENABLE;
Anny hint would be appreciated.
Thanks Erik
