Hi expert,
My customer is studying the ADC PPB module and they have some questions on PPBxZERO, ADCPPBxTRIPHI.LIMITHI and ADCPPBxTRIPLO.LIMITLO.
As described in TRM,
To enable this functionality, first point the ADCPPBxCONFIG.CONFIG to the desired SOC, then write a value to one or both of the registers ADCPPBxTRIPHI.LIMITHI and ADCPPBxTRIPLO.LIMITLO (zerocrossing detection does not require further configuration). Whenever these limits are exceeded, the PPBxTRIPHI bit or
PPBxTRIPLO bit will be set in the ADCEVTSTAT register. Note that the PPBxZERO bit in the ADCEVTSTAT
register is gated by EOC and not by the sign change in the ADCPPBxRESULT register. The ADCEVTCLR
register has corresponding bits to clear these event flags. The ADCEVTSEL register has corresponding bits
which allow the events to propagate through to the PWM. The ADCINTSEL register has corresponding bits
which allow the events to propagate through to the PIE.
Here are two questions:
- how does PPBxZERO work since it is triggered by sign change, however the adc result are all positive?
And what does mean by ‘gated by EOC’
- ADCPPBxTRIPHI.LIMITHI and ADCPPBxTRIPLO.LIMITLO only will trigger respective flag but not effect the ADC sample routine or restrict the ADC sample range? Is my understanding right?
