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TMS320F280025: Internal crystal PLL function configuration

Emma Wang
Expert 5290 points
Part Number: TMS320F280025


Hi Expert,

My customer is using F280025 internal crystal to the main crystal source.

And they have two options to get the 100MHz output.

InitSysPll(INT_OSC1, IMULT_60, REFDIV_2, ODIV_3, PLLCLK_BY_1, SYSCTL_DCC_BASE0);

InitSysPll(INT_OSC1, IMULT_20, REFDIV_2, ODIV_1, PLLCLK_BY_1, SYSCTL_DCC_BASE0);

I found the clock frequences table, and I think the IMULT_60 is also OK since the maximime of f(VCOCLK) is 600M.

But what is your recommended configurations?

BTW, should we use OSC2 instead, since it seems the main clock?

BR

Emma

  • 0
    TI__Mastermind 39620 points

    Hi Emma,

    Yes, please recommend OSC2 instead.  OSC1 is the default clock used for some other purposes (like missing clock).  Note that REFDIV divides the input clock so 1st setup yields a VCOCLK of (10Mhz/2)*60 = 300MHz which is within spec but 2nd setup yields (10MHz/2)*30 = 150MHz which is outside the VCOCLK spec.

    Regards,

    Joseph