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TMS320F280041: Different ADC module sampling the same DAC output: result differences

Sheldon He
Expert 8585 points
Part Number: TMS320F280041

Hi expert,

My customer is testing ADC-DAC internal loopback safety mechanism. They find different ADC core will get different result on sample voltage source.

In F280041 device they convert DACA output with A0, B15 and C15. DACA here is referenced with VREFHI/VSSA while these ADC cores are referenced with the same external 3V voltage.

They get below results in their testing: (numerical)

DAC = 1000 ，ADCA = 1003 , ADCB = 1010 , ADCC = 1014

DAC =2000 ，ADCA = 2001 , ADCB = 2018 , ADCC = 2026

DAC = 3000 ,  ADCA = 3004 , ADCB = 3026 , ADCC = 3037

We see results from ADCB and ADCC shows big difference against ADCA. Is that coming from resonable channel to channel differences?

How do we know if it is normal or not?

Thanks

Sheldon

  • 0
    TI__Guru 60865 points

    Hi Sheldon,

    As far as the difference between the DAC output and the ADC input, you can consult the gain, offset, and linearity specifications for both data converters.  The RSS method can be used to combine these specifications to get an overall TUE for the ADC-to-DAC loopback expected accuracy. 

    However, of more concern I think is the ADC-to-ADC difference.  The relevant specifications would be ADC-to-ADC offset error and ADC-to-ADC gain error.  Since the difference you are seeing is quite a bit larger than these specifications, some investigation is definitely in order:

    • What S+H duration are you using to sample these channels?  Does the difference get smaller when sampled with maximum ACQPS value?
    • How fast are you sampling the loopback connection?  Are you sampling continuously back-to-back (at or near the full MSPS of the ADC), or periodically with some delay in between (e.g. with an ePWM at say 100kHz)?  If you switch to the second method, and reduce the sampling frequency, do the results improve?
    • Have both the ADC and DAC been allowed to fully power up before sampling?
    • Are you sampling the loopback connection simultaneously?  If not, what order are you sampling the loopback connection?  Do the results change when sampling in a different order?  If you are sampling simultaneously, do the results change when sampling sequentially?
    • What circuit are you using to drive the VREFHI input(s)? Is it high-bandwidth and very low impedance?

    I'll also investigate if we have a specification for the expected delta between loopback channels.   

  • 0 in reply to Devin Cottier
    TI__Expert 8585 points

    Hi Devin,

    Thanks for your feedback, we get more findings here and would like to share with you.

    We have DAC test circuit connection like above. We put capacitance to 10nF and resistance to 1k then we get what I mentioned in previous thread,

    When we change resistor from 1k to 10k, the issue in no more existing. (three ADC get almost the same numeric value). Do you have any idea of what happens behind?

    Thanks

    Sheldon

  • 0 in reply to Sheldon He
    TI__Guru 60865 points

    Hi Sheldon,

    There are limits to the size of the capacitive load and the resistive load the DAC can drive.  10nF + 1kohm violates the capacitive loading spec's and reduces the usable range while 10nF + 10kohm only violates the capacitive loading spec'. 

    You might try 10k + 100pF and 1k + 100pF.

  • 0 in reply to Devin Cottier
    TI__Expert 8585 points

    Hi Devin,

    Thanks for your kind reminder.

    BTW, may I know if different result from different ADC internal connected to each other is caused by DAC goes out of the operating conditions? But, why they are different? (They should be connected together at very low impedance, right?)

    Thanks

    Sheldon

  • 0 in reply to Sheldon He
    TI__Guru 60865 points

    Hi Sheldon,

    In the case of a resistance that is too small, the output buffer can't handle the current load, resulting in non-linear behavior of the DAC buffer.

    In the case of an excessively large capacitive load, the DAC buffer may become unstable or may have other issues driving the load. 

    In either case, ADC sampling is a dynamic event (the ADC input is not high impedance) so even small differences between the impedances can be amplified, especially if the ADC driver is weak and has to drive 3 ADCs simultaneously.