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TMS320F280049C: The TMS320F280049C I2C get NAK with the MPU6050(GY-521 board)

WEN LIN HUANG
Prodigy 40 points
Part Number: TMS320F280049C
Other Parts Discussed in Thread: TMS320F28379D, TMS320F28069M, LAUNCHXL-F280049C

While we use TMS320F280049C I2C to communicate with the MPU6050(GY-521 board), we always get NAK.

We also try to use TMS320F280049C PMBus interface to communicate with the MPU6050(GY-521 board), we can communicate with this device normally.

We had discussed with TI Taiwan, and also try to rework the external PU resistor / external capacitor for I2C circuit, modify the communication frequency/duty cycle, get and modify the sample code from TI software resource example, or from TI Taiwan, the test result still fail(NAK).

We also try other C2000 MCUs like TMS320F28069M(control card), TMS320F28379D(launchpad), we can communicate with MPU6050(GY-521 board) through I2C interface normally.

By the way, we also try other I2C device, we can communicate with the device through TMS320F280049C I2C interface, it seems the compatible issue with the MPU6050.

So, after discuss with  TI Taiwan, we would like to post this issue on the TI E2E to get further support to check the root cause of this issue.

The TI FAE we contacted is cs-hsieh@ti.com

We also pass one GY-521 board to him and he can also reproduce the same NAK issue at TI Taiwan side,

The GY-521 board information is as below

www.instructables.com/.../

  • 0
    TI__Expert 4580 points

    Hi,

    The NACK that you are receiving is occurring during the address phase or data phase?

    Also, if you can attach some scope captures when the NACK is coming, it will help us understand the issue better.

    Regards,
    Praveen

  • 0 in reply to Praveen Kumar Ravichandran
    TI__Guru 55700 points

    Hi,

    What is the external pull-up resistor and bus capacitance on the I2C pins when connected to MPU6050?

    I would recommend to have a stronger pull-up and small bus capacitance to say around 50pf.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 40 points

    Hi,

    For external PU resistor, we already try 1K/4.7K/10K/100K

    For the I2C bus capacitor, we try 0.5pF

    Thanks

  • 0 in reply to Praveen Kumar Ravichandran
    Prodigy 40 points

    Hi, 

    For the NAK is during the address phase.

    And below are some wave form

    1. slave address NAK

    1. CLK/DAT with PU 1K resistor

    3. zoom in for signal check

    4. Rising time = 115ns

    5. CLK/DAT with PU 4.7K resistor + bus 0.5pF capacitor

    6. LA decode result

    7. Zoom in for signal check

    8. Rising time = 200ns

    Thanks

  • 0 in reply to WEN LIN HUANG
    TI__Guru 55700 points

    Can you try with 1K pull-up resistor and 50pf bus capacitor?

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 170 points

    hi Manoj, 

    I'm Kai, the co-worker of WEN LIN HUANG, 

    could you help to tell us, the reason for using 1k-ohm / 50p-f ?

    is about the internal circuit of IC (TMS320F280049C),

    or layout of PCB (LAUNCHXL-F280049C),

    or others key points? 

    Sincerely, 

    Kai

  • 0 in reply to Kai Shen1
    TI__Guru 55700 points

    Kai,

    1K pull-up resistor recommended allows the user to work with I2C baud rate 400 KHz with around 300pf bus capacitor.

    50pF bus capacitor is recommended suppress noise on I2C SDA / SCL lines based on Advisory I2C: SDA and SCL Open-Drain Output Buffer Issue in F280049 errata. We are currently running some simulations on this advisory. So, you won't have 50pF bus capacitance recommendation yet. But, we will be updating it errata 1Q 2021.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 40 points

    Hi, Manoj

    After rework 1K pull-up resistor and 50pf bus capacitor, we can communicate with MPU6050(GY-521 board) successfully

    Below is the LA wave form for reference.

    Thanks

  • 0 in reply to Manoj Santha Mohan
    Prodigy 170 points

    hi Manoj, 

    I find 50ns but 50pf directly, in " I2C SDA / SCL lines based on Advisory I2C: SDA and SCL Open-Drain Output Buffer Issue" of F280049 errata. 

    I think the 50ns, means "pulse width of spikes that must be suppressed by the input filter", in I2C Spec. 

    The order of capacitance with pf usually correspond to HF, and the 50ns correspond to 20MHz, 

    I could realize use around pf for 50ns, could you help to explain why the recommendation specific to "50"pf ?

    thank you very much. 

    Sincerely, 

    Kai

  • 0 in reply to Kai Shen1
    TI__Guru 55700 points

    Kai,

    It is great to know that you were able to get I2C communication working with MPU6050.

    As mentioned in I2C: SDA and SCL Open-Drain Output Buffer Issue Advisory, internal timing skew issue causes the outputs to drive a logic-high for a duration of 0–5 ns. The advisory recommends to use series termination resistors to get around the issues mentioned in erratum. In order the eliminate the problem it looks like we need a larger series termination resistor (around 100 ohms) without having bus capacitance. However, have larger series termination resistor is going to reduce the noise margin on VIL limits. So, alternate solution to get around the issue is to include 50pf bus capacitance + 20-25 ohm series resistor solution.

    For your I2C communication problem in your thread, you might got around the issue with small bus capacitance (around 20 - 30 pf). But, I recommended 50pF bus capacitance to reduce the series resistor needed to handle the problem mentioned in errata. Hope this helps.

    Regards,

    Manoj