Other Parts Discussed in Thread: LAUNCHXL-F28027F
Hi
I am using the LaunchXL-F28027F.
I'm trying to trigger ADC sampling through ePWM. I want each ADC sampled at the center of the PWM on pulse. My PWM configuration and ADC configuration is shown below.
I have configured a GPIO interrupt inside adc_isr() to indicate the sampled instances. But when I look at the oscilloscope waveforms I see that the ADC is sampled every other PWM cycle instead of every PWM cycle. How can I fix this? Could you please help?
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///ADC COnfig
EALLOW;
//
// ADCINT1 trips after AdcResults latch
//
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1 Continuous mode
//
// setup EOC2 to trigger ADCINT1 to fire
//
AdcRegs.INTSEL1N2.bit.INT1SEL = 2;
//
// set SOC0 channel select to ADCINA4
//
AdcRegs.ADCSOC0CTL.bit.CHSEL = 4;
//
// set SOC1 channel select to ADCINA4
//
AdcRegs.ADCSOC1CTL.bit.CHSEL = 4;
//
// set SOC1 channel select to ADCINA2
//
AdcRegs.ADCSOC2CTL.bit.CHSEL = 2;
//
// set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first
// then SOC1
//
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
//
// set SOC1 start trigger on EPWM1A, due to round-robin SOC0 converts first
// then SOC1
//
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
//
// set SOC2 start trigger on EPWM1A, due to round-robin SOC0 converts first
// then SOC1, then SOC2
//
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 5;
//
// set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;
//
// set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;
//
// set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
//
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;
//Enable PWM clock here for enabling SOC trigger by ePWM1.
CLK_enablePwmClock(myClk, PWM_Number_1);
EDIS;
//
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
//
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
//
// Select SOC from from CPMA on upcount
//
EPwm1Regs.ETSEL.bit.SOCASEL = 3; // for zero and load triggering
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//PWM Config
void
HRPWM1_Config(Uint16 period, Uint16 CoarseDuty)
{
CLK_enablePwmClock(myClk, PWM_Number_1);
//
// ePWM1 register configuration with HRPWM
// ePWM1A toggle low/high with MEP control on Rising edge
//
PWM_setPeriodLoad(myPwm1, PWM_PeriodLoad_Immediate);
PWM_setPeriod(myPwm1, 300); // Set timer period
PWM_setCmpA(myPwm1, 250);
PWM_setCmpAHr(myPwm1, (1 << 8));
PWM_setPhase(myPwm1, 0x0000); // Phase is 0
PWM_setCount(myPwm1, 0x0000); // Clear counter
PWM_setCounterMode(myPwm1, PWM_CounterMode_UpDown); // Count up
PWM_disableCounterLoad(myPwm1); // Disable phase loading
PWM_setSyncMode(myPwm1, PWM_SyncMode_Disable);
//
// Clock ratio to SYSCLKOUT
//
PWM_setHighSpeedClkDiv(myPwm1, PWM_HspClkDiv_by_1);
PWM_setClkDiv(myPwm1, PWM_ClkDiv_by_1);
//
// Load registers every ZERO
//
PWM_setShadowMode_CmpA(myPwm1, PWM_ShadowMode_Shadow);
PWM_setShadowMode_CmpB(myPwm1, PWM_ShadowMode_Shadow);
PWM_setLoadMode_CmpA(myPwm1, PWM_LoadMode_Zero);
PWM_setLoadMode_CmpB(myPwm1, PWM_LoadMode_Zero);
PWM_setActionQual_CntUp_CmpA_PwmA(myPwm1, PWM_ActionQual_Set);
PWM_setActionQual_CntUp_CmpB_PwmA(myPwm1, PWM_ActionQual_Clear);
//
// MEP control on Rising edge
//
PWM_setHrEdgeMode(myPwm1, PWM_HrEdgeMode_Falling);
PWM_setHrControlMode(myPwm1, PWM_HrControlMode_Duty);
PWM_setHrShadowMode(myPwm1, PWM_HrShadowMode_CTR_EQ_0);
}
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
Thank you,
Shamanth
