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TMS320F28388D: The clock source of CLB

Luke Chen
Expert 5090 points

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hi champs,

As I know, F28388D should support 8 CLB tiles, but TRM shows F28388D only support 4 tiles.

My question is that the clock source of CLB is controlled by PCLKCR17 register, does this mean the clock source of CLB is SYSCLK? What's the maximum clock frequency does F28388D CLB module support? Is it 100MHz or 200MHz please?

Regards,

-Luke

  • 0
    TI__Guru 52040 points

    The F28388D device has 8 tiles.

    The clock for the CLB can be selected from two different source, one of which is SYSCLK 100MHz. This device's CLB can go up to 150 MHz in a new mode called PIPELINE mode, but the support for that will not be released until 1Q21. Luke, there is a BETA release internally if you would like to try it now.

    Nima

  • 0 in reply to Nima Eskandari
    TI__Expert 5090 points

    Nima,

    My question is that if we use SYSCLK as CLB clock source, does it mean we have to set SYSCLK to 100MHz so that CLB works well? So c28x also works at 100MHz system clock?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 52040 points

    No there is a divider in place. With the default driverlib examples, SYSCLK is at 200MHz. CLB clock is at 100MHz. The new TRM will have the pipeline mode + detailed description of the CLB clocking on how to increase the clock to 150MHz.

    But by default, in the C2000Ware support right now, CLB is 100MHz, CPU is running at 200MHz.

    Nima

  • 0 in reply to Nima Eskandari
    TI__Expert 5090 points

    Nima,

    In F2837xD/S, the CLB clock source is form ePWM clock. I remember that the F28004xC CLB clock source is also from ePWM clock, but we have to enable ePWM clock and enable CLBx clock in PCLKCR17 register, is this correct please?

    According to F2838x TRM and your comments, the F2838x CLB clock = SYSCLK/2, not from ePWM clock, is this correct? Is it a fixed divider or programable? Where can I find the information of this CLB clock divider please?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 52040 points

    For F2837xD/S 07x, the EPWM1 clock drives the CLB, and must be enabled.

    In F28004x, F28002x, F2838x, there are CLB clock gates and only the corresponding CLB clock gate has to be enabled. This is show in the beginning of the main function in the CLB examples for these devices vs F2837xS/D 07x devices.

    Nima

  • 0 in reply to Nima Eskandari
    TI__Expert 5090 points

    Nima,

    As the information I got before, for F2837xD/S 07x devices, the ePWM1 clock drives CLB tile1, ePWM2 clock drives CLB tile 2, and so on. Is this correct? Because ePWM clock drive CLB, we are able to scale ePWM clock for different frequency of CLB clock if needed.

    According to your comments, in F28004x, F28003x and F2838x, CLB clock is from SYSCLK, not ePWM clock? Then how can we prescale SYSCLK for different frequency of CLB clock please?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 52040 points

    Yes sorry about that in F2837xD/S each EPWM1-4 drives CLB TILE1-4.

    For F28004x, I am not aware of a clock divider. Only a clock gate. I have never encountered customers wanting to run the CLB at a lower speed.

    For F28002x and F2838x, you have access to clock dividers:

    CLBCLKCTL, you have tile divider control and clock mode control.

    Nima

  • 0 in reply to Nima Eskandari
    TI__Guru 52040 points

    The register name: CLBCLKCTL