Hello,
we got some questions from customer regarding the accuracy of Potenza CMPSS DAC and they described attached.
Regards, Holger
Hi Holger,
Responses to your questions inline:
1. Did they already consider the correct tolerance for CMPSS-DAC?
[FA] If you are looking at the total error from the CMPSS-DAC, you can use the Root Mean Squared approach. Formula below:
However, keep in mind that using RSS is a bit pessimistic as you are very unlikely to find a device that has the worst gain error, offset error and inl. Also, INL error already includes DNL error.
2. How to consider Gain/Offset or all other items from datasheet?
[FA] See above.
3. What is finally minimum Vref range we can achieve to monitor?
[FA] I don't understand what you mean by this. Can you expand?
4. DAC data sheet values “DAC code change” ? What’s meant by that?
[FA] As indicated in the 3rd footnote, within a CMPSS when one comparator trips, it temporarily disturbs the other with the magnitude and duration indicated in the datasheet.
5. Which values and how to consider for Vref monitoring?
[FA] I don't understand what you mean by this. Can you expand?
6. Further question on voltage reference and trim of Buf-DAC. The below table indicates DAC max output is 2.5V when using external voltage reference. Is that true and is there a reason for that?
[FA] 2.5v is the test condition used for the table. Refer to the allowable reference voltage range in the datasheet.
7. On the DAC trim registers, it seems one place in the document indicates it “must be adjusted” and another location states it “should not be modified”. Can you clarify what is our recommendation on this?
[FA] As the trim procedure indicates, if you are using the buffered DAC at 2.5v reference voltage, no adjustment is needed.
