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TMS320F280049C: Configuring ADC with epwm

Jan Buschen
Intellectual 341 points

Part Number: TMS320F280049C

Hello,

I just tried out your example in the driverlib: adc_ex3_temp_sensor to see how to configure the EPWM to trigger my adc with the right frequency.

If I understood the documentation right, I need to configure the period TB:

// periode count
EPWM_setTimeBasePeriod(EPWM1_BASE, 0x0800);

And the counter:

//
// Set counter compare value
EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 0xFFFF);

So I would generate every t = periode * compare_value and event. Where periode depends on the epwm clock frequency, where the divider is initially set to 2? Now no matter what i put into :

EPWM_setTimeBasePeriod(EPWM1_BASE, ANY_VALUE);

The interrupt is always about every 130.000 system clock cycles (freq. 100 MHz). 

So where is my lag of understanding the documentation.

I already watched: (https://training.ti.com/getting-started-c2000-epwm-module)and read the documentation.

  • 0
    TI__Guru 60865 points

    Hi Jan,

    Only the period should control the trigger frequency.  So if the ePWM clock is 1/2 SYSCLK, SYSCLK is 100MHz, and the ePWM period is 1000 cycles, then the trigger should occur every t = (1/100MHz)*2*1000 cycles = 20us (assuming the PWM is in up-count mode...in up-down count mode the trigger period would be roughly twice as long).  If the period is now 2000 counts, the trigger should occur every 40us. 

    As for the compare, this sets the phase of the trigger inside the ePWM period. If the period is 1000 and the compare is 500, then the trigger will occur in the middle of the ePWM period.  If the compare is 900, it'll occur near the end.  If the compare is greater than the period, the trigger will never occur  (so your configuration of this to 0xFFFF doesn't seem right).

    You can also trigger the ADC off of the zero or period match in the ePWM to trigger at the beginning or end of the ePWM counting period if you don't want to configure the compare (these will be the almost the same time in up-count mode).