Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
Launching Cpu2- flash_debug version runs smooth.
Now I made a new .cmd for the Flash cpu1 version (RAM runs excellent) and it is not possible to arrive at main(). You see very fast _c_int00 flashing by upon reset and restart, but then the program runs dead in a estop.
/*deze versie in laatste make*/
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000123, length = 0x0002DD
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2a5 : origin = 0x00E000, length = 0x004000
/* RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000*/
RESET : origin = 0x3FFFC0, length = 0x000002
/* MemCfgRegs.GSxMSEL.all = 0xc003; Globally shared GS0, GS1, GS14, GS15 aan Cpu02*/
/* Flash sectors CPU1 en id CPU2*/
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
PAGE 1 : /* Data Memory */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
/* MemCfgRegs.GSxMSEL.all = 0xc003; Globally shared GS0, GS1, GS14, GS15 aan Cpu02*/
RAMGS6a7 : origin = 0x012000, length = 0x002000
RAMGS8a9 : origin = 0x014000, length = 0x002000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x000FF8
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}
////////////////////////////////////////////////////////////// CPU01
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(8)
.text : >> FLASHB | FLASHC | FLASHD | FLASHE | FLASHF | FLASHG PAGE = 0, ALIGN(64)
codestart : > BEGIN PAGE = 0, ALIGN(8)
/* Allocate uninitalized data sections: */
.stack : > RAMM1, PAGE = 1
.switch : > FLASHB PAGE = 0, ALIGN(8)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.pinit : > FLASHB PAGE = 0, ALIGN(8)
/* Allocate uninitalized data sections: */
.ebss : > RAMGS6a7, PAGE = 1
/* ramdma : > RAMGS2a3, PAGE = 1*/
.esysmem : > RAMLS5, PAGE = 1
.cio : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHF PAGE = 0, ALIGN(8)
corr_tabel : > FLASHN, PAGE = 1, ALIGN(8)
corrtabel : > RAMGS12, PAGE = 1, ALIGN(8)
sttabel : > RAMGS10, PAGE = 1
sygmoid : > RAMGS11, PAGE = 1
ramgs13 : > RAMGS13, PAGE = 1
fifo : > RAMGS8a9, PAGE = 1
tabls : > RAMGS10, PAGE = 1
FLtabls : > FLASHM, PAGE = 1
cpu1tocpu2 : > CPU1TOCPU2RAM, PAGE = 1
cpu2tocpu1 : > CPU2TOCPU1RAM, PAGE = 1
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
/* The following section definitions are required when using the IPC API Drivers NIET combineren met eigen oplossingen!!
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}*/
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
