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TMS320F28388D: Interrupt for UART using with DMA in CM core

Long Pham Tan
Intellectual 391 points

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

hi,

I am using C2000 - F28388D chip, my project is now using CM - Core for communication UART with other device. Number of transfer data is about 100 bytes so I am using UART with DMA.

I config:

 - With UART: 8bit length, no parity, 1 stop bit , no using FIFO, and declare enable interrupt for UART_DMA_TX, RX (by set 2 bits DMATXIM, DMARXIm in UARTIm registrer).

 - With DMA: using 2 channel 8 for UART0_RX, channel 9: for UART0_TX, both channel is setup primary, data size : 8bit ,arbitrate size: 1 byte for each transfer, transfer size: 100 items, basic mode.

My concern: with my config for UART and DMA above When does the interrupt of DMA happen, when a transfer arbitrate size 1 byte complete or transfer total transfer size - 100 items complete?

In the referrence manual of F28388D chapter DMA has mentioned:

"

Depending on the peripheral, the μDMA can indicate transfer completion at the end of an entire transfer or
when a FIFO or buffer reaches a certain level ( Table 49-2 and the individual peripheral chapters). When a
μDMA transfer is complete, a dma_done signal is sent to the peripheral that initiated the μDMA event.
Interrupts can be enabled within the peripheral to trigger on μDMA transfer completion. For more
information on peripheral μDMA interrupts, see the individual peripheral chapters. If the transfer uses the
software μDMA channel, then the completion interrupt occurs on the dedicated software μDMA interrupt
vector (see Table 49-6) "

I understand the interrupt of DMA in this case will be handled by UART interrupt, but so confused when the interrupt signal will be sent to UART, Is that each time when 1 byte arbitrate size transfer complete - 100 interrupts corresponding 100 byte or just  one interrupt when the total 100 byte transfer complete?

Thanks,

Longpt

  • 0
    TI__Expert 4145 points

    Hi Longpt,

    The direct answer would be interrupt of DMA will be triggered for the transfer size which is 100 bytes.

    To understand further you should not put the arbitration size of 100 when not using fifo mode. There are 2 types of attributes for the DMA channel. 1 is single request other is burst request. If the the UART FIFO is not enabled the single and burst request does not have any difference. For RX the DMA will be triggered for every fifo level reached but it will read 100 bytes and trigger interrupt. This will change the content of DMA buffer to DATA byte followed by remaining zeros. 

    To change the attribute of DMA use API UDMA_enableChannelAttribute(UDMA_BASE, UDMA_CHANNEL_UART0_TX, UDMA_CH_ATTR_USEBURST); 

    This will trigger the DMA based on the FIFO level set in UARTIFLS Register and make sure the arbitration size in the DMA is the same value as in fifo level.

    Please refer to section 48.3.9 DMA Operation in the f2838x TRM. You may also want to go through the following example.

    uart_ex2_loopback_udma and udma_ex1_software_trigger in C2000Ware.

    Thanks,

    Yashwant 

  • 0 in reply to Yashwant Temburu1
    Intellectual 391 points

    Hi Yashwant,

    Thanks for your respond, but I still have some concerns below,

    1, For TX , when I do not use FIFO, Is it similar to RX as you mentioned in reply? Is that " For TX DMA will be triggered (single request by UART) for every byte have to be transfered by UART but after DMA transfer 100 bytes from memory to UART data register it will trigger interrupt ==> Am I right?

    2, If I use FIFO, UART will trigger DMA based on the FIFO level set in UARTIFLS Register and  config the transfer size in the DMA is the same value as in fifo level. But the fifo is only 16 byte deep, so the level set is 1/8,1/4,1/2,3/4,7/8 (2 bytes, 4 bytes, 8 bytes, 12 bytes, 14 bytes), a single and burst request from UART will trigger DMA . DMA will trigger interrupt after each time when transfer bytes to or from FIFO buffer done (number of bytes transferred is value which is declared in transfer size). So how can I know when 100 bytes are transfer done?

  • 0 in reply to Long Pham Tan
    TI__Expert 4145 points

    Hi Longpt,

    In the previous reply I've mistaken arbitration size with Transfer size corrected it.

    1. Yes its the same for TX. Interrupt will be triggered for transfer size.

    2. This is a snippet of TRM 

    "When the DMA is finished transferring data to the TX FIFO or from the RX FIFO, a dma_done signal is sent to the UART to indicate completion. The dma_done status is indicated through the DMATXRIS and DMARXIS bits of the UARTRIS register. An interrupt can be generated from these status bits by setting the DMATXIM and DMARXIM bits in the UARTIM register."

    So all you have to do is set transfer size of 100 and set the interrupt mask for DMA in UART to receive interrupt when the transfer is complete.

    I am attaching a code which serves your purpose. It writes 100 bytes to TX using DMA and reads 100 bytes from RX (without fifo) using DMA and an interrupt service routine is called after the 100 bytes are received.

    e2e.ti.com/.../uart_5F00_ex2_5F00_loopback_5F00_udma_5F00_100bytes_5F00_int.c

    Thanks,

    Yashwant 

  • 0 in reply to Yashwant Temburu1
    Intellectual 391 points

    Thanks you very much!

    I now got the understanding!.