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TMS320F28388D: Guidelines for HW design (schematics, PCB)?

AnBer
Mastermind 30395 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: TMDSCNCD28388D, C2000WARE, TPS62420

Team,

Can you please help with the below question?

1) According to the data sheet, each voltage supply pin (VDD, VDDIO) should be decoupled with 100nF each.
Is this a MUST or can nearby supply pins also be combined together? Any concrete advised for this?

2) Is there a breakdown of the VSS connections available, to understand which power supply or function groups they belong to?

3) Is it really necessary to connect a 22µF capacitor between VREFHIx and VREFLOx at the ADC connections for 16-bit conversion (see page 17 of SPRSP14C)?

4)I have seen from different other E2E forum post that the best document for Hardware design duidelines is the datasheet/data manual.
Is it correct?

Also can the TMDSCNCD28388D card (schematics/PCB in C:\TI\c2000\C2000Ware_3_01_00_00\boards\controlCARDs\TMDSCNCD28388D) be considered as good reference for the HW design?
For example is the TPS62420 PMIC handling the appropriate power up/down sequencing for 3V3 and 1V2?

Thanks in advance!

A.

  • 0
    TI__Mastermind 45606 points

    Hi AnBer,

    We recommend following all datasheet guidelines, see my replies below.

    1. I think you're asking if decoupling caps can be shared for pins that are close to each other. If so, I think it's OK to as long as the cap isn't too far away and you include a sufficient number of caps on your board. You can take a look at the TMDSCNCD28388D design for guidance (16 caps on VDDIO and 7 on VDD).
    2. I don't believe we have this to share, but will check and get back to you.
    3. Yes, you should include the caps. See section '20.15.4 Designing an External Reference Circuit' in SPRUII0 for additional details.
    4. Yes the datasheet and TRM are the best documented guidelines we provide at this time. I'd suggest referencing the TMDSCNCD28388D for a good reference design.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    TI__Mastermind 45606 points

    Hi Andrew,

    Getting back to you on #2 we just have the following general information to share. Digital IPs are grounded to chip level VSS and analog IPs to chip level VSSA.

    Can you further explain the need for VSS pin breakdown? This isn't something I've seen asked before, normally the concern is more about separating analog and digital grounding.

    Best,

    Kevin