Hello,
I converted the out file to hex format using the following command:
hex2000.exe -boot -sci8 -a Example_2806xLEDBlink.out -o blinky_new.txt
it converts with the following output:
Translating to ASCII-Hex format...
"Example_2806xLEDBlink.out" codestart ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" ramfuncs ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" .text ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" .cinit ==> (BOOT TABLE)
"Example_2806xLEDBlink.out" .econst ==> (BOOT TABLE)
Then I flash the file using the following command:
serial_flash_programmer.exe -d f2806x -k f28069_sci_flash_kernel.txt -p COM6 -b 9600 -v -a blinky_new.txt
and then get the following output:
C2000 Serial Firmware Upgrader
Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
getting comm state
building comm DCB
adjusting port settings
calling f05_DownloadImage
Downloading blinky_new.txt to device...
Kernel AutoBaud Successful
aa==aa
8==8
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
0==0
62==62
83==83
2==2
0==0
0==0
0==0
0==0
0==0
40==40
0==0
57==57
83==83
b6==b6
0==0
0==0
0==0
50==50
0==0
c==c
fe==fe
40==40
76==76
5==5
.
.
.
Kernel Loaded
Done Waiting for kernel boot...attempting autobaud
Application AutoBaud Successful
(gets stuck here indefinitely)
Please let me know if I am doing anything wrong.
EDIT:
After replacing the command file with "/f28069/common/F28069.cmd", the above mentioned problem fixed and now I am able to upload blinky example firmware to controller but still when i try to upload my firmware, it gets stuck at the same place. is it possible that my firmware is too big like 300KB that it would take soo much time to upload? or is there something wrong with the command file of my firmware, i am pasting it down here, please check that out.
/*
* Copyright (c) 2015-2020, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== TMS320F28069.cmd ========
* Define the memory block start/length for the F28069
*/
/*
* PAGE 0 will be used to organize program sections
* PAGE 1 will be used to organize data sections
*
* Notes:
* Memory blocks on F2806x are uniform (ie same
* physical memory) in both PAGE 0 and PAGE 1.
* That is the same memory region should not be
* defined for both PAGE 0 and PAGE 1.
* Doing so will result in corruption of program
* and/or data.
*/
_Cla1Prog_Start = _Cla1funcsRunStart;
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 : /* Program Memory */
RAML4L : origin = 0x00A000, length = 0x001C00 /* on-chip RAM block L4 */
L03SARAM : origin = 0x008000, length = 0x002000 /* on-chip RAM block L0-L3 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASH : origin = 0x3D8000, length = 0x01FF80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* CSM password locations in FLASH */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
M01SARAM : origin = 0x000000, length = 0x000800 /* on-chip RAM block M0, M1 */
PIEVECT : origin = 0xD00, length = 0x100
L46SARAM : origin = 0x00A000, length = 0x006000 /* on-chip RAM block L4-L6 */
L78SARAM : origin = 0x010000, length = 0x004000 /* on-chip RAM block L7, L8 */
CLARAM2 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
CLARAM0 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
CLARAM1 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L1 */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
/*
* Allocate sections to memory blocks.
* Note:
* codestart user defined section in DSP28_CodeStartBranch.asm
* used to redirect code execution when booting to flash
*
* ramfuncs user defined section to store functions that will be
* copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASH PAGE = 0
.pinit : > FLASH PAGE = 0
.text : > FLASH PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASH PAGE = 0,
RUN = L03SARAM PAGE = 0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart)
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > M01SARAM | L46SARAM PAGE = 1
.ebss : > M01SARAM | L46SARAM PAGE = 1
.data : > M01SARAM | L46SARAM PAGE = 1
.esysmem : > L78SARAM | L46SARAM | M01SARAM PAGE = 1
.cio : > L78SARAM | L46SARAM | M01SARAM PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASH PAGE = 0
.switch : > FLASH PAGE = 0
.args : > FLASH PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASH PAGE = 0,
RUN = L03SARAM PAGE = 0,
table(BINIT)
#endif
#endif
/* Allocate IQ math areas: */
IQmath : > FLASH PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES PAGE = 0, TYPE = NOLOAD
/*
* Uncomment the section below if calling the IQNexp() or IQexp()
* functions from the IQMath.lib library in order to utilize the
* relevant IQ Math table in Boot ROM (This saves space and Boot ROM
* is 1 wait-state). If this section is not uncommented, IQmathTables2
* will be loaded into other memory (SARAM, Flash, etc.) and will take
* up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2 PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/*
* Uncomment the section below if calling the IQNasin() or IQasin()
* functions from the IQMath.lib library in order to utilize the
* relevant IQ Math table in Boot ROM (This saves space and Boot ROM
* is 1 wait-state). If this section is not uncommented, IQmathTables2
* will be loaded into other memory (SARAM, Flash, etc.) and will take
* up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3 PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
.scratchpad : > CLARAM0, PAGE = 1
.bss_cla : > CLARAM0, PAGE = 1
.const_cla : > CLARAM0, PAGE = 1
dclfuncs : LOAD = FLASH, PAGE = 0,
RUN = RAML4L PAGE = 0
dcl32funcs : LOAD = FLASH, PAGE = 0,
RUN = RAML4L PAGE = 0
Cla1Prog : > FLASH,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
Cla1DataRam0 : > CLARAM0, PAGE = 1
Cla1DataRam1 : > CLARAM1, PAGE = 1
Cla1DataRam2 : > CLARAM2, PAGE = 1
CLA1mathTables : > CLARAM1,
LOAD_START(_Cla1mathTablesLoadStart),
LOAD_END(_Cla1mathTablesLoadEnd),
LOAD_SIZE(_Cla1mathTablesLoadSize),
RUN_START(_Cla1mathTablesRunStart),
PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM0,
PAGE = 1
}
Thanks,
Najeeb
