I am adapting this processor into an existing application, where the 28377S is the slave and receives commands from and transmits data to the master.
The receipt of data is working fine.
Transmission of data from the 28377S slave to master follows the following format:
where S = Start, SA = Slave Acknowldge, NA = NACK, and P = Stop.
This is also working, however when the code enters the "Read Back Data" segment (after receiving the second Slave Address Byte with R/W = 1 as shown above) I write my data to I2CA I2CDXR register. What the master receives is the data I sent on the previous cycle. If I issue another read command to the slave I then receive the correct data.
The TRM description of the I2CSTR XSMT bit has the following statement:
" If new data is not transferred in time, the previous data may be re-transmitted on the SDA pin."
This appears to be the problem I'm facing. I am using the TX FIFO to transmit the data, but I suspect I've got a register set improperly.
Thanks in advance for any insight.
