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Need for ASP and NASP inside ISR?

Mokan Kanna
Intellectual 580 points

Before entering the ISR of the application, the processor saves on stack a set of registers like acc,p,dp which are necessarily push of 32 bit registers. How is it that the hardware does those 32 bit push'es without  proper alignment of stack? Is it a must that the ASP / NASP instruction at entry and exit if the ISR does any 32 bit stack operation? I am puzzled and concerned about any unnecessary load (of these 2 instructions) on a high speed ISR.

Can someone clarify? Thanks.  

Sayee

_myIsr:

ASP

....

NASP

IRET ; return from interrupt

  • 0
    Intellectual 580 points

    As an additional observation, I am reading in page 3-14 of spru430e to realize that hardware does a 32 bit alignment by adjusting the SP before the PUSH'es are executed. Then there is absolutely no need of ASP / NASP in ISR. There are couple places in this documentation (spru430e ) which induce this doubt, where a code sample to describe NASP instruction talks specifically about its applicability in a ISR . That is really misleading.

    ISR is the only place where ASP/NASP are not needed for 32 bit stack operations. We can really save unnecessary load there.

     If we disassemble the compiled ISR code written in 'C', we see  ASP/NASP inserted by the compiler which is totally not needed. This puts a big doubt in our minds.

    Can someone clarify if ?

    Thanks

     

    Sayee

  • 0 in reply to Mokan Kanna
    Expert 2355 points

    Having recently ported an RTOS to the C28 family, I came across this very issue.  After studying it hard I found a solution which works. 

    This is my explanation / interpretation of the documents:

    Normal 0 MicrosoftInternetExplorer4

    Since the data is stored in 32-bit words they need alignment to an even address.  Therefore if the stack is at an odd address when the interrupt is called the SP is increased by one.   In order to balance/indicate the addition/lack of addition, one is added to the SP at the end, if the one has not been added prior, i.e. if the SP was at an even address in the first place.  This can cause some issues.

    Now this leaves the stack odd aligned if the stack was evenly aligned previously and even aligned if it was odd previously.   This is to indicate the stack alignment done during the automatic context save.  When the IRET is called it checks whether the stack is odd or even aligned and uses this information so it can reverse this automatic stack alignment to leave the SP the same as it was before the interrupt.

    Now with regards to ASP / NASP, as stated prior the stack may be odd aligned when the interrupt code is started.  If any 32-bit  PUSHing and POPping are to be done, (and they should be in an interrupt) the stack should be even aligned so using an ASP command is necessary.  The NASP is just there to cancel it out at the end.

    Hope that explains why the ASP and NASP are there and what the stack is doing during an interrupt context save.  If you have any questions I (or anyone else) will try to answer them.

     

    Tim