TMS320F280049: TMS320F280049 interrupt at CTR=ZERO with HRPE = 1

Hi Nima,

Thank you for your reply. 

Yes, I'm trying to to use HRPWM, with period and phase control by modifying TRREM to realize phase shift in the interrupt routine triggered by ePWM1 CTR=ZRO. The Master(ePWM1) seems good, but I found some jitter on the slave(ePWM2) at some specific micro-step, say, PRD:PRDHR = 20.2 seems good, but PRD:PRDHR = 20.6 will show some jitter on the slave pwm signal (with CMPA = PRD/2, AQ using CAU set and CAD clear the pwm).

As you mentioned above. 

"The interrupt is triggered exactly at TBCTR=ZERO and ofcourse a couple of cycles before the ISR handler starts executing."

In the ISR handlerthe TRREM value of both the ePWM1 and ePWM2 will be modifed as showed bellow. I want to know how this is possible to modify the TRREM value just in time for a cpu runing at 100MHz with a couples of cycles before the ISR handler and a couples of instructions to run before modify TRREM register? Or does the TRREM have a shadow register?

    EALLOW;
    if (LoadAction == 1)
    {
        //
        // This should also write to GLDCTL2 of PWM2
        //
        (*ePWM[1]).GLDCTL2.bit.OSHTLD = 1;

        //
        // TBCTR phase load on SYNC (required for updown count HR control)
        //
        (*ePWM[2]).TBCTL.bit.PHSEN = TB_ENABLE; 

        //
        // TBCTR phase load on SYNC (required for updown count HR control)
        //
        (*ePWM[2]).TBPHS.bit.TBPHS = temp_PHS;
        (*ePWM[2]).TRREM.bit.TRREM = 0x100 + temp_REM; 
        (*ePWM[1]).TRREM.bit.TRREM = 0x100; 

        LoadAction = 0;
    }
    else
    {
        (*ePWM[2]).TBCTL.bit.PHSEN = TB_DISABLE;
    }

    EDIS;

Regards,

Ruj

TRREM does not have a shadow register.

Subrahmanya Akshaya Jain Manish Bhardwaj

Can you comment on the TRREM value update? I do not have the technical information on the TRREM workaround.

Hi Nima, 

I still have some question about the interrupt trigger time and I think there is something different beacuse of the fraction part of the period.

As you mentioned here :

"So HRPWM works using "delay" elements. Meaning the HRPWM delay is not connected to a clock. There are actual delay elements which will delay the signal and you can enable a different number of elements to delay the edges of the PWM signals."

and above:

"That is the coarse step = ZERO event of the TBCTR. It has nothing to do with the high resolution part of the EPWM.

Again, the jitter, if it is part of the HR and is not present on the EPWM withouth HR, no it wont be there on when the ISR is generated. "

It seems the MEP works independently with normal resolution PWM module. The Integer part of period is determined by Timer-Counter & TBPRD register with a clock and the fraction part of period is determined by the MEP delay(with numbers shown in REM).

Consider a situation like this: PRD:PRDHR = 10.1, the integer part is 10, so the PWM without HR works like period with 10. However, the real full period is 10.1, with time goes, the fraction part will accumulate every cycle and eventually bigger than 1, like below.

Does the coarse part will handle the integer produced by the accumulate part of fraction ?  Will this affect the interrupt trigger period?

Regards,

Ruj

Ruj,

For that level of detail, let me take this to design to get an accurate answer for your specific question.

Nima

Nina and Subrahmanya, Thank you very much for your explain.