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TMS320F28379D: TX FIFO Interrupt behavior

Yannick Bertrand
Prodigy 120 points

Part Number: TMS320F28379D

Upon inspection of the example code in C2000Wate (driverlib\f2837xd\examples\cpu1\spi\spi_ex2_loopback_fifo_interrupts.c) for SPI loopback, I don't quite understand what is the logic begind the SPITXINT interrupt.

First, the technical manual states :

"In FIFO mode, the SPITXINT behavior is similar to the SPIRXINT. SPITXINT is generated upon a match
condition between the current transmit FIFO status (TXFFST) and the transmit FIFO interrupt level
(TXFFIL). If TXFFST is less than or equal to TXFFIL, the transmit FIFO interrupt flag (TXFFINT) will be
set. SPITXINT will be triggered in the PIE block if TXFFINT is set and the transmit FIFO interrupt is
enabled in the SPI module (TXFFIENA = 1)"

1- Why would the interrupt trigger if TXFFST < TXFFIL? If TXFFST is zero, isn't the FIFO empty? If the FIFO is empty, why would the interrupt be generated?

2- Is the purpose of the interrupt is to fire whenever the FIFO queue is empty (or below it's level) in oder to keep the FIFO "filled", or is the purpose of the interrupt to send the data (i.e. call SPI_writeDataNonBlocking).

3- How is TXFFST increased? Debugging the example code spi_ex2_loopback_fifo_interrupts.c, I see that TXFFST is constantly zero. How is TXFFST supposed to ever change i.e. in which conditions is it incremented and in which conditions is it decremented?

Thanks!

  • 0
    TI__Mastermind 32655 points

    Hi Yannick Bertrand,

    Yannick Bertrand said:
    1- Why would the interrupt trigger if TXFFST < TXFFIL? If TXFFST is zero, isn't the FIFO empty? If the FIFO is empty, why would the interrupt be generated?

    TX interrupt is an indication to the application that it has completed transmitting the data in the TX FIFO and is available for the next set of data to be transmitted. It indicates that FIFO is empty or has lesser contents than than the configured value, so that the next set of data can be filled in.

    Yannick Bertrand said:
    2- Is the purpose of the interrupt is to fire whenever the FIFO queue is empty (or below it's level) in oder to keep the FIFO "filled", or is the purpose of the interrupt to send the data (i.e. call SPI_writeDataNonBlocking).

    You are right. It is to interrupt the application when the TX FIFO is empty or below a certain level and expects the ISR to fill in the next set of data. You can use SPI_writeDataNonBlocking function to fill the data

    Yannick Bertrand said:
    3- How is TXFFST increased? Debugging the example code spi_ex2_loopback_fifo_interrupts.c, I see that TXFFST is constantly zero. How is TXFFST supposed to ever change i.e. in which conditions is it incremented and in which conditions is it decremented?

    TXFFST is an indication of number of data available in the TX FIFO. It will reduce by 1 as and when the data is transmitted. It might be difficult to see that in the debugger view. Whenever you write to the TX FIFO, it is transferred to the shift register for sending. If SPI in the process of sending, the data will remain in the FIFO and the TXFFST will remain 1. If you add one more data to the TX FIFO and the SPI has not yet completed sending the first data, this too will remain TX FIFO and TXFFST will become 2. So, it depends on the how fast you fill the TX DATA, also, when you halt the debugger, the SPI might have completed the transfers and that's why you see it as 0 always.

    Hope this helps!

    Regards,

    Veena