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TMS320F280049: DCC and clock slip detection realted questions

Sheldon He
Expert 8585 points
Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE

Hi expert,

1. We are using F280049 while F28388's datasheet told me SYSPLL slip detection itself is not recommended for new design. May I know the reason behind this?

Does it also applicable to F280049 devices?

2. From TRM snip below, I think valid0 should never be less than 10, while our driverlib code gives valid0seed value of 4. Could you explain this a bit more?

Thanks

Sheldon

  • 0
    TI__Genius 15385 points

    Hi Sheldon,

    Answers to your questions:

    1. Yes, SLIPS is not supported on F2838x. We have a new analog PLL on F2838x which does not report SLIP, user needs to rely on DCC which will be more accurate in determining the drift in PLL frequency, and that is the recommended way of validating PLL frequency.

    F280049 has a different PLL, and it does report SLIP so it is still supported.

    2. You are correct Valid0 minimum will be 10 based on TRM and yes the driverlib code is not updated with the information in TRM, and it is still showing 4. This has been addressed already, next C2000Ware version that will get released will have this updated. There is no reliability concern with using 4. 

    Best Regards,

    Nirav

  • 0 in reply to Nirav Ginwala
    TI__Expert 8585 points

    Hi Nirav,

    Additionally, we find the time between external clock failure and NMI interrupt raising could be as long as 800us plus which make this protection quite non-realtime. Could you help us know the reason behind?

    The red line are crystal signals and we use blue line (DAC output) to indicate differnet conditons. SYS_PLL_SLIP is quickly indicated while NMI comes much later. Could you just use a DCC to detect slip or missing clock instead of using a SLIP detection?

    Thanks

    Sheldon

  • 0 in reply to Sheldon He
    TI__Genius 15385 points

    Hi Sheldon,

    Missing Clock Detect (MCD) detects the crystal failure and generates CLOCKFAIL signal which generates the NMI interrupt to the system. But the detection time for MCD is 8192 INTOSC1 cycles, which is ~800us, which correlates to what customer is seeing. 

    For faster response time, PLL_SLIP flag will be a good indicator for F280049, it generates a soft interrupt to PIE (INT12.13), which needs to be serviced through ISR routine which should put the system in safe state.

    DCC is also a good option, but the response time depends on the configuration of window. For gross fails where we are not checking for accuracy of the clock, DCC window can be reduced for faster response time.

    Best Regards,

    Nirav

  • 0 in reply to Nirav Ginwala
    TI__Expert 8585 points

    Excellent answer!