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TMS320F28035: Question about move full bridge topology peak current control

Gabriel Wang1
Genius 4375 points
Part Number: TMS320F28035

Our application is 1.8kW, output 24V ,and use move full bridge topology peak current control .What we do is move to the full bridge topology peak current control power supply (1.8kW, output 24V), refer to the TI official routine "HVPSFB_PCMC" and the User Guide, if you meet the following problems, please help:

1. Using the official code of "HVPSFB_PCMC" : Can the peak current run without load? When the no-load current is 0, can a comparison event occur? Can control the peak current?

2. Currently, according to the logic in the reference document, we load 4A on the electric band. At this time, the output of 20V can be stable; at the output of 24V, the EPWM2 driver has serious jittering. We don't know what the cause is, so we wonder if there is a problem with the control logic and ask for help.

Note: The period before and after the judgment is interrupted in EPWM1. CLA controls the voltage loop, and its output is used as the peak current control input.

  • 0
    TI__Genius 15685 points

    Hi Gabriel,

    1. It should still work and should not trigger any protection. But I don't think we have done more tests without load. When the current is zero, there is no comparison event, the PWM will be reset to certain scheme which maintains zero phase shift. 

    2. Is this jittering happening under the open voltage loop(closed peak current loop)?  There should not be a control logic for this design. But maybe it is related to some corner case. We have to look into it step by step.

    Regards,

    Chen

  • 0 in reply to Chen Jiang ti
    Genius 4375 points

    Hi Chen

    Thanks for your reply

    1.As you saying" When the current is zero, there is no comparison event, the PWM will be reset to certain scheme which mainstays zero phase shift."My quesion is that if not both load and no-load output should be peak current control.As long as it is the peak current control should have more events, such as I 24 v output stability, idle time I input voltage rise slowly, the output will rise slowly, when it comes to an 24 v output in theory should be stable output, the input voltage if continue to increase, it should need more events to phase shift PWM action to maintain the output voltage stability, you say the PWM will be reset to certain scheme which maintains a zero phase shift how to do?

    2.I have solved the second problem by changing the slope of the slope. Thank you!

  • 0 in reply to Gabriel Wang1
    TI__Genius 15685 points

    Hi Gabriel,

    1. I was talking more about the startup process when there is no load. For the no load condition during operation, please take a look at the thread below 

    "

    I understand your test conditions now. When I say low load, I mean less than 0.3A on the HVPSFB kit (it could be lower, but this number is a bit conservative). When you are operating under no load or very low load condition, the operation should change to voltage mode control or duty/burst mode. This allows the output voltage to be regulated to ~12V. With PCMC, there is a need for blanking. This blanking implies a minimum duty value for the power stage. Under very low load conditions, this minimum duty value might be enough to make the o/p voltage go very high (like 18V in your case). This high voltage can be disastrous for the power stage.

    Unfortunately, this change from PCMC to VMC/duty mode and back has not been implemented in the default software. This has been done before but here it is left up to the users to implement their own algorithms for this function.

    "

    Regards,

    Chen