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TMS320F28388D: LSPCLK configuration

Amulrass Vazhumuni
Intellectual 435 points
Part Number: TMS320F28388D


Hello,

I have a question on LSPCLK configuration. Can the Low Speed Peripheral clock divider LSPCLKDIV can be configured with different values for CPU1 and CPU2? For Example: CPU1 configures LSPCLK = SYSCLK/2, but CPU2 can configure for SYSCLK/4 or so.

Or,

Is LSPCLKDIV is a common configuration and cannot be done individually from each CPUs?

Best Regards

Amulrass V

  • 0
    TI__Expert 5430 points

    Hi,

    The LSPCLKDIV configuration is a part of the CLK_CFG_REGS which can be configured by either CPU1 or CPU2 based on the who owns the Clock semaphore(refer to the CLKSEM register description). For CPU2 to control this configuration, CPU2 has to first grab the semaphore by configuring the CLKSEM register. 

    Hope this helps.

    Please click on the "verify answer" button if this response has resolved your query.

    Thanks & Regards

    Pramod