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TMS320F28388D: AD and DA

huijin Wang
Intellectual 270 points
Part Number: TMS320F28388D

Dear

I am testing AD and DA function with the controlCARD based on TMS320F28388D.

And I configure the DACB with the reference voltage “VREFHI”， I connect the pin marked as "ADCINA0" and the pin marked as"ADCINA1", which means the pin DACBOUT is connected to the pin ADCINA0.

But I found that when I set the DACB value with a digital  number for example"2048" , the AD result would be 2112, when I set "3000", AD result would be "3158", And what is the root cause for this problem?

Do I need to make any additional calibration?

  • 0
    TI__Guru 60865 points

    Hi huijin,

    What S+H duration are you using (set by acqps field of the SOC configuration register)?  Each time the ADC samples there will be a kick-back to the DAC output, so the DAC will require some time to settle. 

    The full-scale settling spec' for the DAC in the device datasheet is 2us (which is much larger than you will need for the load transient) and the minimum ADC S+H time is 75ns (which will be too fast). You might need to experiment a little bit to determine where you get good settling, but I'd recommend starting at 300-400ns. 

  • 0 in reply to Devin Cottier
    Intellectual 270 points

    Thank you for your quick response.

    I have tested some values such as 75ns,150ns, 300ns, 450ns and so on, and it does have some effects on the AD results.

    when the sample window time is more than 300ns then the influence of the window time will be small.

    the difference between the digital value of the DAC and that of the ADC result will be less than 10 LSBs. Is this within the tolerance？

    By the way. could you please  explain the two parameters meaning below in the red frame， what do they mean?

  • 0 in reply to huijin Wang
    TI__Guru 60865 points

    Hi Huijin,

    10 LSBs is probably within tolerance.  You'd want to refer to the gain, offset, and INL specifications on both the DAC and ADC to determine the approximate expected error.  

    I believe load transient settling time is the time for the DAC to settle when the DAC's load changes.  This is actually exactly what is happening when the ADC samples (the ADC S+H capacitor and switch resistance is added to the DAC output when the S+H switch closes for ADC sampling) so this is probably a good value to use for ADC S+H when sampling the DAC.  

    The full-scale output settling time is the time for the DAC to settle when you set a new DAC output value (and this one is the worst-case where you transition from near zero-scale to near full-scale).  This would be a good time to wait between when you change the DAC output and when you sample the ADC (if you want to see the ADC sample the final settled DC value that you set the DAC to).  

  • 0 in reply to Devin Cottier
    Intellectual 270 points

    Hi  Devin Cottier，

    Thank you for your  detailed explanation！