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Internal Flash Full-Speed?

BrandonAzbell
Guru 64630 points

Other Parts Discussed in Thread: TMS320F28035

Posted on behalf of

Using CCS, what code is being executed from RAM when the Flash is enabled and what is the reason this is done.  Are there performance limitation of the Flash that won't allow code to run at full clock speed from the Flash?

  • 0
    TI__Guru 64630 points

    It is important to be more specific about what code you are referencing.  CCS is the Integrated Development Environment that provides the debugger environment, project workspace, configuration of the code generation tools, etc.  It is not software running on the target.

    The number of wait states to be used with the flash are described in Table 6-45 of the TMS320F28035 datasheet.

  • 0 in reply to BrandonAzbell
    Expert 1240 points

    Hi, I had asked Scott this question. Specifically, I am looking at the FOC code in the Low Voltage motor kit.  It appears that for a Flash Build, code is being copied into RAM for execution.  So, RAM has 0 wait states.  I'm new to the 28035 and it's not clear when wait states come into play with the flash.  Is it when the processor is clocked beyond a minimum (like faster than 40MHz, then a Flash wait state of 1 is needed)?  

     

  • 0 in reply to tom prohaszka
    TI__Guru* 93410 points

    tom prohaszka said:
    code is being copied into RAM for execution.  So, RAM has 0 wait states.

    Correct

    tom prohaszka said:
    I'm new to the 28035 and it's not clear when wait states come into play with the flash.  Is it when the processor is clocked beyond a minimum (like faster than 40MHz, then a Flash wait state of 1 is needed)?  

    Yes.  In the data manual Brandon mentioned, take a look at Table 6-44. Flash/OTP Access Timing.  This gives how fast the flash can be accessed.  In this case 40ns.  Any access that is faster requires the CPU allow more time.   The table Table 6-45. Minimum Required Flash/OTP Wait-States at Different Frequencies shows this calculation for different frequencies.  The formula used can be found under the table.

    Note that the flash has a wide prefetch mechanism that improves linear code performance.   That is, not every instruction the CPU executes will see the impact of the waitstates. 

    Regards,

    -Lori