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TMS320F28388D: Synchronizing Sigma Delta to PWM

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hello there,

I have a topic regarding the synchronization feature of the Sigma-Delta module in the TMS320F28388D. I have serveral Delta-Sigma modulators connected to the controller (AMC1306, AMC1106 and AMC1305)

I implemented the following configuration for PWM1:

  • ePWM is running at 100 MHz
  • Up-counter with ValueTop = 2559. This leads to a carrier with period of 25,6us
  • In Event Trigger Module SOCA is configured to trigger when CTR=ZERO

The capture compare unit eCAP3 is configured to produce a 10MHz clock signal. This signal is distributed to the different modulators and to the sigma delta clock inputs SD1_C1 and SD2_C1 of the TMS320F28388D.

The delta sigma units are configured like this:

  • Modulator Mode 0 (Modulator clock rate equals the modulator data rate)
  • Modulator clock for all sigma delta units is SD1_C1 resp. SD2_C1
  • Data filters set to SINC2 filter
  • Oversampling ratio is set to 128
  • Data representation is 16-Bit
  • The filters are configured to sync on a SOCA event of PWM1

The timing is in principle like this:

Data from the sigma delta modules is requested right after CTR = Zero event of PWM1. The behavior I see now is, that data is correct as long as the sync on SOCA is disabled. As soon as I enable synchronization only invalid data can be captured from the Sigma Delta modules (voltage values vary in range of 30V when input is 0V). My question is now, if the synchronization can be done in this way? Is it possible to resync the data filter in every second cycle? From my point of view the oversampling ratio counter is only synchronized one time right at the beginning. Afterward it should already be "in sync" when the SOCA event triggers to reset the counter. Or is synchronization more than just resetting the DOSR counter?

Hopefully I was able to describe this complex configuration with this short paragraph.

Regard,
Michael Kettler

  • Michael,

    With PWM, you have configured ValueTop = 2559, this resets the SDFM filter channel every 25.6 us. Whenever, filter channel resets, you have to make sure to wait for latency of sinc filter + 5 SD-Cx cycles before you read the filter results. This would mean that after SDSYNC event, you have to wait for 25.6 us + 500 ns = 26.1us.

    But, since SDFM is reset every 25.6us you are not allowing enough time to read the filter results. You either need to increase ValueTop (or) reduce OSR settings.

    I would urge you to look into sdfm_ex4_pwm_sync_cpuread example available in C2000Ware.

    Path: <C2000Ware>\device_support\f2838x\examples\cpu1\sdfm

    With below SDFM configuration:

    SD-Cx freq = 10 MHz

    Filter Type = Sinc2

    OSR          = 128

    Data rate   = 128 / 10 MHz  =  12.8 us

    Latency of Sinc filter = Order of Sinc filter x data rate

                                     = 2 x 12.8 us = 25.6 us

    5-SD-Cx cycles = 5 / (10*10^6) = 500 ns

    Regards,

    Manoj



  • Dear Manoj,

    your answer was very helpful. So what we did now is, to synchronize the filter only once at the beginning and then stop the synchronization.

    Our idea is now that the counters will stay synced, as the clock source for the PWM and the SDFM are the same. So there is no need to synchronize permanently.

    What I did not find in the reference manual or datasheet by now, is the 5-SD-Cx cycles that are needed after synchronization. Is it written somewhere?

    Regards,

    Michael

  • Micheal,

    What I did not find in the reference manual or datasheet by now, is the 5-SD-Cx cycles that are needed after synchronization. Is it written somewhere?

    Please check the CAUTION available in Pg:2954 in SDFM chapter.

    Regards,

    Manoj