I am using the TMS320F28379D as a SPI slave. I have code running to the point where I can receive my test data plenty fine, but the data I am expecting to be sent out by the Delfino is never being sent. The data I do see getting sent out appears to be an echo of the received data, but shifted by a single word. I am currently using a dummy 6 word array for both my master and slave. I can provide any register information or scope traces if needed.
Can someone please review my setup code to make sense of what's going on? I am expecting to see my sdata clocked out as my master is sending me the test array of words.
This is my Delfino setup code:
/// Defines the FIFO trigger level in number of words
#define SPI_SUPER_FIFO_LVL 1
/// Defines the number of words to transfer in a single burst
#define SPI_SUPER_BURST SPI_SUPER_FIFO_LVL
/// Defines the number of bursts to transfer
#define SPI_SUPER_TRANSFER_SIZE 6
// Globals
#pragma DATA_SECTION("ramgs0"); // TODO - does this need to be mapped?
uint16_t sdata[6] = { 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F };
#pragma DATA_SECTION("ramgs1"); // TODO - does this need to be mapped?
uint16_t rdata[6] = { 0x00 };
// Function Prototypes
__interrupt void SPI_MS_to_SUP_TX_DMA_Interrupt( void );
__interrupt void SPI_MS_to_SUP_RX_DMA_Interrupt( void );
/// \author Bryan Radke
/// \brief Initializes the SPI interface to the supervisor processor
/// \param none
/// \return none
///
/// Initializes a DMA slave setup. The supervisor is the master.
void Init_SPI_MS_to_SUP( void )
{
// SPI module must be disabled before configuration
SPI_disableModule( SPIA_BASE );
// SPI clock does not matter since we are the slave. Setup SPI for 16bit data size.
SPI_setConfig( SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0, SPI_MODE_SLAVE, 3000000, 16 );
// We are communicating with the supervisor processor so loopback needs to be disabled
SPI_disableLoopback( SPIA_BASE );
// Enable the FIFO for configuration
SPI_enableFIFO( SPIA_BASE );
// Clear any pending FIFO interrupts before setup/enabling new interrupts
SPI_clearInterruptStatus( SPIA_BASE, SPI_INT_TXFF | SPI_INT_RXFF );
// Setup the TX and RX FIFO to trigger when a single word has been transmitted/received
SPI_setFIFOInterruptLevel( SPIA_BASE, SPI_FIFO_TX1, SPI_FIFO_RX1 );
// Enable the TX and RX FIFO interrupts
//SPI_enableInterrupt( SPIA_BASE, SPI_INT_TXFF | SPI_INT_RXFF );
// Configuration is complete so enable the SPI module
SPI_enableModule( SPIA_BASE );
// Setup DMA channel 5 for sending data to the supervisor
DMA_configAddresses( DMA_CH5_BASE, (uint16_t *)(SPIA_BASE + SPI_O_TXBUF), sdata );
// Configure the TX DMA burst size based on the FIFO levels used
DMA_configBurst( DMA_CH5_BASE, SPI_SUPER_BURST, 1, 0 );
// Configure the TX DMA transfer size based on the data to send and the burst size
DMA_configTransfer( DMA_CH5_BASE, SPI_SUPER_TRANSFER_SIZE, 1, 0 );
// Configure the TX DMA for continue trigger mode based on TX of data
DMA_configMode( DMA_CH5_BASE, DMA_TRIGGER_SPIATX, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT );
// Configure the TX DMA to interrupt at the end of transmission
DMA_setInterruptMode( DMA_CH5_BASE, DMA_INT_AT_END );
// Register the TX DMA interrupt handler
Interrupt_register( DMA_CH5_BASE, &SPI_MS_to_SUP_TX_DMA_Interrupt );
// Enable the TX DMA interrupt
DMA_enableInterrupt( DMA_CH5_BASE );
// Enable the TX DMA to allow a start of transfer
DMA_enableTrigger( DMA_CH5_BASE );
// Setup DMA channel 6 for receiving data from the supervisor
DMA_configAddresses( DMA_CH6_BASE, rdata, (uint16_t *)( SPIA_BASE + SPI_O_RXBUF ) );
// Configure the RX DMA burst size based on the FIFO levels used
DMA_configBurst( DMA_CH6_BASE, SPI_SUPER_BURST, 0, 1 );
// Configure the RX DMA transfer size based on the data to send and the burst size
DMA_configTransfer( DMA_CH6_BASE, SPI_SUPER_TRANSFER_SIZE, 0, 1 );
// Configure the RX DMA for continue trigger mode based on RX of data
DMA_configMode( DMA_CH6_BASE, DMA_TRIGGER_SPIARX, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT );
// Configure the RX DMA to interrupt at the end of transmission
DMA_setInterruptMode( DMA_CH6_BASE, DMA_INT_AT_END );
// Register the RX DMA interrupt handler
Interrupt_register( INT_DMA_CH6, &SPI_MS_to_SUP_RX_DMA_Interrupt );
// Enable the RX DMA interrupt
DMA_enableInterrupt( DMA_CH6_BASE );
// Enable the RX DMA to allow a start of transfer
DMA_enableTrigger( DMA_CH6_BASE );
}
__interrupt void SPI_MS_to_SUP_TX_DMA_Interrupt( void )
{
Interrupt_clearACKGroup( INTERRUPT_ACK_GROUP7 );
}
__interrupt void SPI_MS_to_SUP_RX_DMA_Interrupt( void )
{
if ( rdata[0] != 0 )
{
rdata[0] = 0;
}
Interrupt_clearACKGroup( INTERRUPT_ACK_GROUP7 );
}
