- When running at 60 MHz sysclock, the data sheet indicates a wait state of 2 for flash random and 2 for flash page access. Does this imply that ALL flash access will be delayed now by 2 clocks?! That is, every instruction fetch (assuming single cycle instructions) from Flash is delayed by 2 clocks. Does this imply my effective MIPS is now only 30 MIPS for a 60MHz clock? The demo code for FOC actually is using a wait state value of 3, is there a reason for this? The microchip part we are using now is running at 40MHz and does not have wait states.
-- The FOC performance data is specified as:
For the Dual Axis Kit these optimizations allow for the following on 60 MHz Piccolo F28035:
Each FOC Axis @ 10 KHz = ~12 MIPS
Is this 10KHz operation a linear interpolation, such that if I run at 20KHz for the FOC, we would use 24 MIPs? 30KHz would be 36 MIPs?
Is this 10 KHz based on PWM Frequency? It's not clear.