TMS320F28335: Does TMS320F28335 SCI FIFO use the transmit/receive buffer?

Hi Joon Woo,

Joon Woo Lee said:

"With the FIFO enabled, TXSHF is directly loaeded after an optional delay value (SCIFFCT), TXBUF is not used.".

This is explaining the internal structure of the SCI module, nothing that the user has to actually configure for proper functionality. In this situation TXBUF is the one-word transmit buffer of the standard SCI that just functions as a transition buffer between the transmit FIFO and shift register. 

Joon Woo Lee said:

"When FIFO mode is enabled for SCI, characeters written to SCITXBUF are queued in to SCI-TXFIFO and the characters received in SCI-RXFIFO can be reead using SCIRXBUF".

Even in FIFO mode, data is written to the SCITXBUF register, this data will then get placed into the TX FIFO and data received that is held within the RX FIFO can be read using SCIRXBUF. Looking at a software example within C2000Ware might help clear this up. I would suggest looking at C:\ti\c2000\C2000Ware_version\device_support\f2833x\examples\scia_loopback_interrupts

Joon Woo Lee said:

I know what polling is, interrupt is, FIFO is but in the SCI, what the difference? Especially, Interrupt and FIFO.

For polling, what you are essentially doing is checking if there is any data received by checking the RXRDY bit of the SCIRXST register. This is more of a "manual" check within your program which could take up a lot of CPU bandwidth depending on how frequently you check for new data.

Once you enable TX/RX interrupts, an interrupt will be generated when a new character is ready to be read from the SCIRXBUF register (RXRDY is set), or when the transmit data buffer register, SCITXBUF, is ready to receive another character (TXRDY is set). This allows your program to be more efficient by removing the need to check for new data yourself or check to see if you can write new data.

The intention of FIFO interrupt itself is to reduce the CPU overhead by just reading the FIFO only when the FIFO receives certain user configured number of bytes. In FIFO mode the TX interrupt is triggered whenever the transmit FIFO status (TXFFST) bits match (equal to or less than) the interrupt trigger level bits TXFFIL and the RX interrupt is triggered whenever the receive FIFO status (RXFFST) bits match (equal to or greater than) the interrupt trigger level bits RXFFIL. That being said, in FIFO mode you can choose to only trigger an interrupt after you have transmitted or received a certain number of bytes instead of the non-FIFO method of triggering an interrupt every time a new character can be read or transmitted. 

Best Regards,

Marlyn