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Hello,
I’m using the C2000 DIMM Experimenter’s kit with the TMS320F28335 microcontroller.
I want to create 6-PWM signals phase shifted to each other. In particular:
- PWM 1 is the master for the synchronization
- PWM 2 is shifted by 120° respect PWM 1
- PWM 3 is shifted by 240° respect PWM 1
- PWM 4 is in phase to PWM1+gui_phase_shift
- PWM 5 is shifted by 120° respect PWM 4
- PWM 6 is shifted by 240° respect PWM 4
Where gui_phase_shift can vary in range [0°, 90°] or in range [270°, 360°].
When gui_phase_shift is the range [270°, 360°], I can’t get any PWM signal from the PWM4 module. It’s seem that the maximum value allowed is for 268°: for higher degrees there’s no signal.
How can I solve this problem?
Here there are the initialization for PWM1 and PWM4 module:
void init_pwm1 (void)
{
/* TBPDR = 1/2* freq_sysclkout / (freq_pwm * CLKDIV * HSPCLKDIV) */
EPwm1Regs.TBPRD = 536u; /* PWM Period = 140kHz */
EPwm1Regs.TBCTL.all = 0x0000u;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 3u;
EPwm1Regs.TBCTL.bit.CTRMODE = 2u;
EPwm1Regs.TBCTL.bit.PRDLD = 1u;
/* TBCLK = SYSCLKOUT/(HSPCLKDIV *CLKDIV) */
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x000u;
EPwm1Regs.TBCTL.bit.CLKDIV = 0x000u;
/* Phase-shift configuration */
/* (TBPHS / TBPRD) * 360° = (phase_shift)° */
EPwm1Regs.TBPHS.half.TBPHS = 0x0000u;
EPwm1Regs.TBCTL.bit.PHSEN = 0u;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1u;
EPwm1Regs.AQCTLA.all = 0x0000u;
EPwm1Regs.AQCTLA.bit.CAU = 1u;
EPwm1Regs.AQCTLA.bit.CAD = 2u;
EPwm1Regs.DBCTL.bit.OUT_MODE = 3u;
EPwm1Regs.DBCTL.bit.POLSEL = 2u;
EPwm1Regs.DBFED = 50u;
EPwm1Regs.DBRED = 50u;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 1u;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 1u;
EPwm1Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD/2;
EALLOW;
EPwm1Regs.TZCTL.bit.TZA = 2u;
EPwm1Regs.TZCTL.bit.TZB = 2u;
EDIS;
}
void init_pwm4 (void)
{
/* TBPDR = 1/2* freq_sysclkout / (freq_pwm * CLKDIV * HSPCLKDIV) */
EPwm4Regs.TBPRD = 536u; /* PWM Period = 140kHz */
EPwm4Regs.TBCTL.all = 0x0000u;
EPwm4Regs.TBCTL.bit.FREE_SOFT = 3u;
EPwm4Regs.TBCTL.bit.CTRMODE = 2u;
EPwm4Regs.TBCTL.bit.PRDLD = 1u;
/* TBCLK = SYSCLKOUT/(HSPCLKDIV *CLKDIV) */
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x000u;
EPwm4Regs.TBCTL.bit.CLKDIV = 0x000u;
/* Phase-shift configuration */
/* (TBPHS / TBPRD) * 360° = (phase_shift)° */
EPwm4Regs.TBPHS.half.TBPHS = gui_phase_shift;
EPwm4Regs.TBCTL.bit.PHSEN = 1u
EPwm4Regs.TBCTL.bit.PHSDIR = 0u;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 1u;
EPwm4Regs.AQCTLA.all = 0x0000u;
EPwm4Regs.AQCTLA.bit.CAU = 1u;
EPwm4Regs.AQCTLA.bit.CAD = 2u;
EPwm4Regs.DBCTL.bit.OUT_MODE = 3u;
EPwm4Regs.DBCTL.bit.POLSEL = 2u;
EPwm4Regs.DBFED = 50u;
EPwm4Regs.DBRED = 50u;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 1u;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 1u;
EPwm4Regs.CMPA.half.CMPA = EPwm4Regs.TBPRD/2;
EALLOW;
EPwm4Regs.TZCTL.bit.TZA = 2u;
EPwm4Regs.TZCTL.bit.TZB = 2u;
EDIS;
}
Andrea,
as a debug step I would recommend removing the dead band for now.
What TBPHS value are you inputting for a 270 degree phase shift?
It looks like you are using up-down count mode, please confirm.
It looks like you are also using CAD to set the PWM output high, so you should look particularly close at that event.
I'm a little curious if you are applying a dead band that is longer than your pulse width, but that doesn't appear to be true either.
Regards,
Cody
Hello Cody,
yes I'm using up-down count mode.
I'm using the following formula to calculate the phase shift used in the TBPHS register: TBPHS = (TBPRD * 270°) / 360° , where TBPRD is equal to 1071 because of the up-down count configuration.
I try different things and I think I solved the problem: instead of using CAD and CAU to set the PWM output high and low respectively, I used ZRO and PRD.
With this configuration there's no problem at all. The problem remain only if I use CAD and CAU to manage the PWM output.
Do you have any idea why?
Regards,
Andrea
Andrea,
Andrea Milani said:I'm using the following formula to calculate the phase shift used in the TBPHS register: TBPHS = (TBPRD * 270°) / 360° , where TBPRD is equal to 1071 because of the up-down count configuration.
So for 270 you would input 803.25 into TBPHS? If you were counting up after a sync event this would cause all events to be missed and if you continue to sync every period it would likely never allow any output. So knowing because of this I suppose you would be counting down after a sync event, correct?
Please note that your TBPRD is defined as 536, I recognize that you entire PWM period length is 1071, but for simplicity lets only use TBPRD when referring to the bit field structure. Let's call 1071 your PWM period length.
If you were counting down after a sync event then this would potentially cause a CAU event to be missed if your CMPA value is in the discontinuity region. This is because for every period ePWM4 receives a sync signal from ePWM1 its counter value jumps from whatever the current value is to the value loaded in TBPRD, 803 in the case of a 270 degree shift. While the counter is counting down from 803 to TBPRD we know that no events will trigger because CMPA is less than TBPRD.
To further explain this the synchronization pulse comes from ePWM1 every 1071 cycles in that time ePWM4 would have counted down from 803 and then counted up to ~250. When the next sync pulse comes in the counter jumps from ~250 to 803 again. So CAU events will be missed when CMPA is larger than the highest TBCTR value while counting up.
If you wish to do phase shifts larger than 180 degrees please change the counter direction and input the phase shift required above 180 degrees.
TBCTR = period and zero always happen because you've shifted when in the period the discontinuity is.
Regards,
Cody
Cody,
thank you for the explanation.
Cody Watkins said:So for 270 you would input 803.25 into TBPHS? If you were counting up after a sync event this would cause all events to be missed and if you continue to sync every period it would likely never allow any output. So knowing because of this I suppose you would be counting down after a sync event, correct?
Yes, for 270 the input is 803.25 and I configured the PWM module to count down after a sync event in both test carried out: the one with the CAU and CAD, and the one with PRD and ZRO.
Cody Watkins said:Please note that your TBPRD is defined as 536, I recognize that you entire PWM period length is 1071, but for simplicity lets only use TBPRD when referring to the bit field structure. Let's call 1071 your PWM period length.
You're right, but it's correct to use 1071 to determine the input value to the TBPHS register?
Cody Watkins said:To further explain this the synchronization pulse comes from ePWM1 every 1071 cycles in that time ePWM4 would have counted down from 803 and then counted up to ~250. When the next sync pulse comes in the counter jumps from ~250 to 803 again. So CAU events will be missed when CMPA is larger than the highest TBCTR value while counting up.
If you wish to do phase shifts larger than 180 degrees please change the counter direction and input the phase shift required above 180 degrees.
I think I get it. So, if I want to keep the CAU and CAD configuration for phase shift larger than 180 degrees, I have to change the direction after a synchronization event to up?
Regards,
Andrea
Andrea,
Andrea Milani said:You're right, but it's correct to use 1071 to determine the input value to the TBPHS register?
You can use it for the calculation of your phase shift in clock cycles, but I would recommend never inputting a value larger than TBPRD into your TBPHS register. It can be done, and it will work under certain conditions but it is up to the user to fully understand this and ensure that their system will never operate in this region.
Andrea Milani said:So, if I want to keep the CAU and CAD configuration for phase shift larger than 180 degrees, I have to change the direction after a synchronization event to up?
Correct I had suggested that you do this.
Regards,
Cody
Cody,
as you suggested I changed the configuration of the PWM modules to the following:
void init_pwm1 (void)
{
/* TBPDR = 1/2* freq_sysclkout / (freq_pwm * CLKDIV * HSPCLKDIV) */
EPwm1Regs.TBPRD = 536u; /* PWM Period = 140kHz */
EPwm1Regs.TBCTL.all = 0x0000u;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 3u;
EPwm1Regs.TBCTL.bit.CTRMODE = 2u; /* Up-Down count mode */
EPwm1Regs.TBCTL.bit.PRDLD = 1u;
/* TBCLK = SYSCLKOUT/(HSPCLKDIV *CLKDIV) */
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x000u;
EPwm1Regs.TBCTL.bit.CLKDIV = 0x000u;
/* Phase-shift configuration */
/* (TBPHS / TBPRD) * 360° = (phase_shift)° */
EPwm1Regs.TBPHS.half.TBPHS = 0x0000u;
EPwm1Regs.TBCTL.bit.PHSEN = 0u; /* Master module */
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1u; /* CTR = Zero: time-base */
EPwm1Regs.AQCTLA.all = 0x0000u;
EPwm1Regs.AQCTLA.bit.CAU = 1u; /* Force EPWMxA output low */
EPwm1Regs.AQCTLA.bit.CAD = 2u; /* Force EPWMxA output high */
EPwm1Regs.DBCTL.bit.OUT_MODE = 3u; /* Dead-band enabled */
EPwm1Regs.DBCTL.bit.POLSEL = 2u; /* Active high complementary */
EPwm1Regs.DBFED = 50u; /* Dead-band falling edge delay */
EPwm1Regs.DBRED = 50u; /* Dead-band rising edge delay */
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 1u;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 1u;
/* counter compare generate the events described in the AQCTL register */
EPwm1Regs.CMPA.half.CMPA = EPwm1Regs.TBPRD/2;
EALLOW;
EPwm1Regs.TZCTL.bit.TZA = 2u;
EPwm1Regs.TZCTL.bit.TZB = 2u;
EDIS;
}
void init_pwm4 (void)
{
/* TBPDR = 1/2* freq_sysclkout / (freq_pwm * CLKDIV * HSPCLKDIV) */
EPwm4Regs.TBPRD = 536u; /* PWM Period = 140kHz */
EPwm4Regs.TBCTL.all = 0x0000u;
EPwm4Regs.TBCTL.bit.FREE_SOFT = 3u;
EPwm4Regs.TBCTL.bit.CTRMODE = 2u; /* Up-Down count mode */
EPwm4Regs.TBCTL.bit.PRDLD = 1u;
/* TBCLK = SYSCLKOUT/(HSPCLKDIV *CLKDIV) */
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x000u;
EPwm4Regs.TBCTL.bit.CLKDIV = 0x000u;
/* Phase-shift configuration */
/* (TBPHS / TBPRD) * 360° = (phase_shift)° */
EPwm4Regs.TBPHS.half.TBPHS = gui_phase_shift;
EPwm4Regs.TBCTL.bit.PHSEN = 1u; /* Enable phase shift */
EPwm4Regs.TBCTL.bit.PHSDIR = 1u; /* Count Up after sync */
EPwm4Regs.TBCTL.bit.SYNCOSEL = 1u;
EPwm4Regs.AQCTLA.all = 0x0000u;
EPwm4Regs.AQCTLA.bit.CAU = 1u; /* Force EPWMxA output low */
EPwm4Regs.AQCTLA.bit.CAD = 2u; /* Force EPWMxA output high */
EPwm4Regs.DBCTL.bit.OUT_MODE = 3u; /* Dead-band enabled */
EPwm4Regs.DBCTL.bit.POLSEL = 2u; /* Active high complementary */
EPwm4Regs.DBFED = 50u; /* Dead-band falling edge delay */
EPwm4Regs.DBRED = 50u; /* Dead-band rising edge delay */
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 1u;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 1u;
EPwm4Regs.CMPA.half.CMPA = EPwm4Regs.TBPRD/2;
EALLOW;
EPwm4Regs.TZCTL.bit.TZA = 2u;
EPwm4Regs.TZCTL.bit.TZB = 2u;
EDIS;
}
I switched to CAU and CAD and, for PWM4 module, I changed the PSHDIR to count up. Furthermore, for the calculation of the phase shift I used TBPRD = 536 in the formula : TBPHS = ((phase shift)*TBPRD)/360°.
In this way, I expect that for TBPHS=TBPRD the PWM1 and PWM4 signals should be in phase.
I run this example and what I get is that the two PWM signals are phase shifted by 180 degrees.
So, I'm doing something wrong again or I don't understand something in your previous answers?
Sorry to bother you again, Cody.
Regards,
Andrea
Andrea,
zero out your phase shift, apply the count up after sync event change. at this point you should see that your signals are 180 degrees out of phase, correct?
At this point begin incrementing TBPHS slowly and you should be able to see this signal slow shift relative to ePWM1. If you do this I believe the phase shifting should be easier to understand.
Regards,
Cody