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TMS320F28375S: ePWM Glitch

Gobind Singh1
Intellectual 640 points

Part Number: TMS320F28375S
Other Parts Discussed in Thread: TMS320F280049C

Hi,

I have a strange problem in the ePWM module. I see a glitch in the PWM waveforms when there is a jump in compare value from less than max counter to greater than max counter.

ePWM configuration:

Up-Down Counter mode

ePWM clock 100MHz

Max period: 2500 (This gives me a pwm frequency 20KHz)

PWM outputs: Active low complementary

I did a test with PWM running at constant duty cycle with compare value 2450, and then manually updated the compare value to 2550. I could see a glitch on the signal.

Screetshot below. 

 Another test was done with PWM running at constant duty cycle with compare value 2450 and then going up in smaller steps like 2480, 2499, 2500, 2501 and 2550. I did not see glitch on the signal.

I tried this on different PWM modules, the results were same. So is this a bug in the module?

CCS Version 10.1

I have seen few posts in e2e forum about the ePWM glitch, but I think my problem was not part of that.

Thank you.

  • 0
    TI__Mastermind 26390 points

    Hi Gobind,

    Can you please re-attach your figure? It didn't seem to go through.

    What are you action qualifier settings?

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Intellectual 640 points

    Hi, 

    I have re-attached the screenshot. Ignore the purpule line. Blue is ePWMA and Green is ePWMB. They are configured in Active Low Complementary mode.

    Action Qualifier Settings:

    AQCTLA.bit.CAU = AQ_CLEAR;
    AQCTLA.bit.CAD = AQ_SET;

    Thank you.

  • 0 in reply to Gobind Singh1
    TI__Mastermind 26390 points

    Hi Gobind,

    Thank you for re-attaching the image. I do see the glitch that you are referring to now. It appears to happen twice, is this consistent?

    You also mentioned that you update the compare values manually, are you doing this through the expression window in CCS, or where in your code do the compare values change? 

    Also, are you doing shadow loading? Is this occurring on zero, period, both? It would help if I could see the rest of your initialization code.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Intellectual 640 points

    Hi Marlyn,

    Yes, the glitch is very consistent.

    I change the compare values through the expression window.

    It is a shadow loading happing at both zero and period.

    I did a further investigation on this problem. I wrote pwm code for a different controller: TMS320F280049C. And I found that the glitch is present for this microcontroller also. So, there is something in the ePWM module.

    Important point is, it happens only when the pwms are configured as "Active Low Complementary". In case of "Active High Complementary", there is no glitch on the ePWMA output, but there is a glitch on ePWMB output.

    Thank you.

  • 0 in reply to Gobind Singh1
    TI__Mastermind 26390 points

    Hi Gobind,

    Could you please provide me with the rest of your initialization code? I'll try to recreate it from my end and figure out what is going on.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Intellectual 640 points

    Hi Marlyn,

    Below are the settings I used. 

    TBCTL.bit.PHSDIR = 0;
    TBCTL.bit.PRDLD = 0;
    TBCTL.bit.CTRMODE = UP_DOWN_COUNT_MODE;
    TBCTL2.bit.PRDLDSYNC = LOAD_ON_ZERO;

    TBCTR = 0;
    TBPRD = 2500;

    CMPCTL.bit.LOADAMODE = C_LOAD_ON_ZERO_OR_P;
    CMPCTL.bit.LOADBMODE = C_LOAD_ON_ZERO_OR_P;
    CMPCTL.bit.SHDWAMODE = 0;
    CMPCTL.bit.SHDWBMODE = 0;

    DBCTL.bit.DEDB_MODE = 0;
    DBCTL.bit.IN_MODE = 0;
    DBCTL.bit.POLSEL = ACTIVE_LOW_COMPLEMENTARY;
    DBCTL.bit.OUT_MODE = 0x3;
    DBRED.bit.DBRED = DB_2us;
    DBFED.bit.DBFED = DB_2us;

    AQCTL.bit.LDAQAMODE = C_LOAD_ON_ZERO_OR_P;
    AQCTL.bit.LDAQBMODE = C_LOAD_ON_ZERO_OR_P;
    AQCTLA.bit.CAD = 2;
    AQCTLA.bit.CAU = 1;

    Test scenario:

    (ePWM clock is 100MHz, so 2500 TBPRD in up-down count mode will give me a pwm of 20KHz, period of 50us)

    1. Load and run the code with constant duty cycly.

    2. Update the compare A value to 2400 in expressions window. (This will give a waveform with very low duty cycle - around 2us - because of Active Low configuration)

    3. Set the oscilloscope to trigger if the pulse width is greater than 10us, and set it to single capture.

    4. Update the compare A value to 2600 in expressions window.

    5. The oscilloscope should have triggered and the last pulse width on the scope will be just above 50us.

  • 0 in reply to Gobind Singh1
    Intellectual 640 points

    Another update:

    If the cmp values are updated in the below sequence, there is that glitch present.

    1. 2499

    2. 2501

    But if the cmp values are updated in the below sequence, there is no glitch:

    1. 2499

    2. 2500

    3. 2501

    Thank you.

    Gobind Singh

  • 0 in reply to Gobind Singh1
    TI__Mastermind 26390 points

    Hi Gobind,

    Thank you for providing the rest of your initialization. Please allow a day for me to test this on my system. I will reply back once I've duplicated the issue.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Mastermind 26390 points

    Hi Gobind,

    I was able to go to the lab to test this out with an oscilloscope, and replicate the glitch that you were seeing.  

    What I believe is happening is the following:

    Your shadow to active load is happening during a zero or period event. Your glitch indicates that two events are missed: CAU and CAD. 

    Now, in your pulse (the glitch), the output goes high (meaning that a CAU event occurred (clear), the output is in complementary mode). The next event is TBCTR=TBPRD, at which your new CMPA value is loaded (CMPA > TBPRD). Now the next CAU or CAD event will not occur until the next time TBCTR=TBPRD because CMPA is now greater than TBPRD. Once the next TBCTR=TBPRD event occurs the CAD action should have priority and take effect.

    One way to minimize this is to only load CMPA on a zero event not zero and period so that you don't miss a CAD event.

    Let me know if that was not clear enough or you have any questions.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Intellectual 640 points

    Hi Marlyn,

    Thank you for the detailed explanation. I did not understand this part:

    Marlyn Rosales Castaneda20 said:

    Now the next CAU or CAD event will not occur until the next time TBCTR=TBPRD because CMPA is now greater than TBPRD. Once the next TBCTR=TBPRD event occurs the CAD action should have priority and take effect.

    Why does CAD action occurs at event (TBCTR=TBPRD)? As per my understanding, CMPA value is loaded at (TBCTR=TBPRD) and the CAD or CAU actions occur only at (TBCTR=CMPA). Since CMPA is now higher than TBPRD, CAD or CAU actions should never occur and the waveform should remain high.

    Thank you

    Gobind Singh

  • 0 in reply to Gobind Singh1
    TI__Mastermind 26390 points

    Hi Gobind,

    When CMPA or CMPB are set to something higher than TBPRD the actions will still occur but when TBCTR=TBPRD. Take a look at the following table within the Technical Reference Manual (TRM). There is a small typo on the header. The first column should be for 'CAU/CBU' not 'CAD/CBD'.

    There is also a priority table that describes the priority of events:

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Intellectual 640 points

    Got it.

    Thank you very much for the quick reply.

    Regards

    Gobind Singh

  • 0 in reply to Gobind Singh1
    TI__Mastermind 26390 points

    My pleasure, hope this clears up your issue!

    Best Regards,

    Marlyn