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TMS320F28069: Flash Memory Read Disturb Error

Akihiko Fujinaka
Expert 3505 points

Part Number: TMS320F28069
Other Parts Discussed in Thread: TMS320F280049

Hello expert,

Our cutomer asked the following questions for TMS320F28069 and TMS320F280049 devices.

1. Are their any possibility to occur the Flash ROM Read Disturb Error in case of the each devices power on/off sequence?

Please tell the number limitation if these devices has.

2. I found the Flash Data retention duration is 20 years for F280049, 15 years for F28069.

It will never occur any bit failure for each duration, is this correct?

Regards,
A.Fujinaka

  • 0
    TI__Genius 15385 points

    Hi,

    Below answers to your questions:

    1. I assume you are asking for any power up or power down sequence requirements affecting Flash read operation? What type of Read disturb scenario is customer concerned about? Typically brownout event during Flash Read operation does not change the integrity of Flash data.

    2. Yes, but please account for Junction temperature as mentioned in the Datasheet. 20 years on F280049 is for Tj=85C, and 15 years on F28069 is for Tj=55C.

    Best Regards,

    Nirav 

  • 0 in reply to Nirav Ginwala
    TI__Expert 3505 points

    Hello Nirav,

    I received the feedback from my customer.

    1. Customer shows one scenario, the read disturb will not occur and 15 years R/W funciton is OK even if the power on/off cycles happen 650 times per day?

    2. Thanks for your answer.

    Regards, A.Fujinaka

  • 0 in reply to Akihiko Fujinaka
    TI__Genius 15385 points

    Hi Fujinaka,

    As per design there is no limitation in number of times you can power cycle the device. R/W function should work fine, but this scenario has not been validated.

    Best Regards,

    Nirav

  • 0 in reply to Nirav Ginwala
    TI__Expert 3505 points

    Hello Nirav,

    my customer recognizes this read disturb issue is the general issue for all the Flash memories, they want to know why TI think there is no limitation?

    Regards,  A.Fujinaka

  • 0 in reply to Akihiko Fujinaka
    TI__Genius 15385 points

    Hi Fujinaka,

    Worst case for Flash Read disturb is mainly due to number of Write/Erase cycles that can cause Stress Induced Leakage Current also known as Read disturb failure. 

    Along with power cycles does the customer also plan to do same amount of Write/Erase operation? We do have Data sheet limit for number of W/E cycles. 

    I can double check with the experts internally to see if there is any limitation related to power cycling that can cause Flash read disturb. 

    Best Regards,

    Nirav

  • 0 in reply to Nirav Ginwala
    TI__Genius 15385 points

    Hi Fujinaka,

    I checked internally with the experts, and as I mentioned there is no concern of Read Disturb related to Power Cycling. Assuming customer is not exceeding the data sheet limit for Write/Erase cycles, and also Flash Write/Erase operations during each power cycle are not terminated prematurely, meaning there is no brownout event condition. Please refer to note in the data manual related to brownout condition.

    Best Regards,

    Nirav

  • 0
    TI__Expert 3505 points

    Hello Nirav, 

    Our customer read the following page,
    en.wikipedia.org/.../Flash_memory
    They recognized, there needs some methodology to avoid this issue even if TI explained no problem, so could you please tell what method is used to avoid it?

    Regards, A.Fujinaka

  • 0 in reply to Akihiko Fujinaka
    Guru 92251 points
    Akihiko Fujinaka said:
    They recognized, there needs some methodology to avoid this issue even if TI explained no problem, so could you please tell what method is used to avoid it?

    The link to Wikipedia about Read disturb is for NAND flash.

    While I can't find it explicitly documented, since the TMS320F28069 and TMS320F280049 devices allow execute-in-place (XIP) the devices are presumably using NOR flash.

  • +1 in reply to Chester Gillon
    TI__Guru* 85110 points

    Akihiko,

    I appreciate the customer's concern to make sure that they are using the device correctly.

    The flash on these devices is integrated into the device itself and not an external memory and would not be bound by considerations that are applicable to generic off the shelf flash ICs.

    We typically don't share physical implementation details of our devices beyond those in the DS that are needed to use the device.

    The customer should proceed with the assumption that so long as they operate the device within the tolerances specified in the device DS it will perform as expected in their system/use.

    Chester,

    A very astute observation on your part regarding the XIP nature of the flash. Slight smile

    Best,
    Matthew