LAUNCHXL-F28379D: Setting up Dead-Band

Hi Dan,

We have some software examples to help showcase the functionality of the dead-band module, this might help. I am not sure if you are using driverlib or bit-field format so here are the directories for both in which you can find the dead-band examples:

C:\ti\c2000\C2000Ware_version\device_support\f2837xd\examples\cpu1

C:\ti\c2000\C2000Ware_version\driverlib\f2837xd\examples\cpu1\epwm

All of the bits you mentioned are within the DBCTL register of the dead-band module. Please take a look at the DBCTL register within the Technical Reference Manual for descriptions of all of the bits you mentioned.

Best Regards,

Marlyn

I am trying to set up PWM1A and PWM1B to form a leg in an inverter with dead band. I have set the AQCTLA and AQCTLB being inverts to each other. Is this needed or I can use the polarity select control to create an inverse of PWM1A and not use AQCTLB?

Hi Dan,

Dan8 said:

I have set the AQCTLA and AQCTLB being inverts to each other. Is this needed or I can use the polarity select control to create an inverse of PWM1A and not use AQCTLB

If you plan to configure the polarity select control (POLSEL) field of the deadband module then you don't need to use AQCTLB to set the inverse.

Also our digital power SDK has real configuration examples for power conversation that could be beneficial for your application!

Best Regards,

Marlyn

Thanks. I have managed to set up the dead band.

By using POLSEL to obtain the inverse of OutA on OutB, on startup the output OutB is at a high level (1) since OutA is at low (0). I would like both outputs to be at low on startup, since a continuous high output on OutB will provide a short path on the converter output. Is there a way to do this using POLSEL? or there is the need to use AQCTLB in this case?

Thanks

Dan

Hi Dan,

One way to get both of your outputs at a low level during start up while still being able to configure POLSEL is to utilize the trip zone submodule. You can do a trip zone software force (take a look at the TZFRC register) to force an OST or CBC trip and make your output low. After start up, you can clear the force.

Best Regards,

Marlyn

Hi,

I am using AQCSFRC to force continuous low on output and then release in a Start/Stop ISR but it still does not work.

Is there a way to apply RED on both PWM1A and PWM1B at the same time? This way I would set up AQCTLA and AQCTLB inverse to each other to leave separate, apply RED on both and not use POLSEL.I think this would keep both OutA and OutB low at startup and also low when stopping the converter within my Start/Stop ISR.

Hi Dan, 

Have you tried to implement the trip zone software force?

Alternatively you could use the action qualifier submodule to inverse your outputs, but a rising edge delay cannot be applied to both outputs. You would need to either select output A or output B.

Best Regards,

Marlyn

Tried to implement the trip zone and causing a trip with EPwm1Regs.TZFRC.bit.OST = 1.

However, this is causing random switching after pressing the start switch (shown below). I am placing the trip first thing before setting the PWM parameters, then clearing within an ISR when pressing a start switch, and trip again when pressing the switch to stop, also within the ISR. (Yellow - PWM1A, Violet - PWM1B). At the moment I am switching with 50% duty cycle.

.

Hi,

I have also noticed that every time I start the PWM running I am having PWM1B high for 2us, before starting switching at the duty cycle. (Shown in the diagram below).

Hi Dan,

Is clearing the trip the only thing you are doing within your start switch ISR?

Best Regards,

Marlyn

Hi,

The start/stop ISR deos the below, depending on the state of the converter.

To start I run these:

    if (EPwm1Regs.TZFLG.bit.OST == 1)
       asm(" EALLOW");
       EPwm1Regs.TZCLR.bit.OST = 1;
       EPwm1Regs.TZOSTCLR.all = 1;
       asm(" EDIS");

    EPwm1Regs.AQCSFRC.all = 0x0000;     // Action-qualifier continuous s/w force register
    EPwm2Regs.TBCTL.bit.CTRMODE = 0x0;  // Enable the timer in count up mode - used for ADCs
    EPwm1Regs.TBCTL.bit.CTRMODE = 0x0;  // Enable the timer in count up mode

When stopping:

    asm(" EALLOW");
    EPwm1Regs.TZFRC.bit.OST = 1;       // Force Trip PWM1 - force low on output
    asm(" EDIS");
    EPwm1Regs.AQCSFRC.all = 0x0005;     // Force continuous low on output - Action-qualifier continuous s/w force register
    EPwm2Regs.TBCTL.bit.CTRMODE = 0x3;  // Disable the timer - used for ADCs

    EPwm1Regs.CMPA.bit.CMPA = 0;    // Set duty cycle to 0 to start again
    EPwm1Regs.CMPB.bit.CMPB = 0;    // Set duty cycle to 0 to start again

    asm(" EALLOW");
    //--- Force Task 8 to clear to zero the controller and duty cycle
        Cla1Regs.MIER.all = 0x0081;            // Enable CLA interrupt 8
        asm("  IACK  #0x0080");                // IACK - CLA task force instruction
        asm("  RPT #3 || NOP");                // Wait at least 4 cycles
        while(Cla1Regs.MIRUN.bit.INT8 == 1);   // Loop until task completes

    //--- Enable CLA Task 1 interrupt and disable Task 8 interrupt
        Cla1Regs.MIER.all = 0x0001;        // Enable CLA interrupt 1 (and disable interrupt 8)
    asm(" EDIS");

Hi Dan,

I know you are clearing the CMPA/CMPB values once you stop but depending if you have shadow loading or not this might not be taking effect right away and possibly attributing to your random switching at startup. What I would suggest is looking at the SOFTPRES2 register. You can set the epwm modules in reset meaning that all registers are returned to their reset states. When you are ready to start the epwm module again then you can call your initialization and clear the SOFTPRES2 bits. This should give you a clean start with everything at a known state.

Best Regards,

Marlyn

Hi,

I am not using shadow loading. Also, the high period on 1B is resulting also on the very first startup after switch on, not only when stopping and re-starting.

Hi,

To isolate the issue I have removed the dead band and outputted 1A and 1B separately from AQCTLA and AQCTLB, providing an output inverse to each other according to the CMPA value. The high 200us period on 1B still remains.

The structure of my program is: PWM2 controls the operation of the ADCs which in turn operate a CLA task. The value of the ADCs are normalized and any control is worked out in this CLA. The controllers are disabled at the moment and I am outputting a fixed duty cycle value from the CLA for these testing purposes. Another CLA task is used to clear the variables in the first CLA task. The second CLA task is operated once when initializing (power up the converter) and then disabled. This second CLA task is operated again within the stop ISR, as can be seen from the previous code.

I am initializing both PWM1 and PWM2 at power on but keep both PWM timers disabled. Then I am enabling these timers within the start ISR as can be seen from the previous code. I have done this to prevent the PWM and ADCs to operate. Especially the ADC and CLA sampling and working with unwanted values, which cause issues in the controllers.

Now, I have discovered that if the PWM2 timer is enabled in up count at the initialization stage, PWM1 outputs the correct duty cycle on both 1A and 1B without the 200us ON period. I am suspecting that when enabling the timer for PWM2 (controlling ADCs and CLA) within the start ISR, the CLA output (duty cycle value in this case) is taking these 200us to be provided in the beginning. This is a problem,because I do not want the CLA to run before I press the start button for the reasons explained before.

Hi Dan,

Dan8 said:

if the PWM2 timer is enabled in up count at the initialization stage, PWM1 outputs the correct duty cycle on both 1A and 1B without the 200us ON period

What are your action qualifier events?

Dan8 said:

when enabling the timer for PWM2 (controlling ADCs and CLA) within the start ISR, the CLA output (duty cycle value in this case) is taking these 200us to be provided in the beginning

Instead of clearing the trip zone force when you enter the start ISR have you considered clearing it once the CLA has outputted a duty cycle value?

Best Regards,

Marlyn

Yes if PWM2 timer is enabled in up count at the initialization stage, the PWM1 output will not produce the 200us period, however this will also make the ADCs work which will then eventually produce an erronous duty cycle output from the controllers within the CLA.

For the second point, how can I know when the CLA is ready with a value?

I have managed to remove the 200us from the first start after power on (diagram 1), however I am still getting a high period on 1B output at consecutive start-ups of the converter (diagram 2). This high period varies up to 200us. I noticed that this is happening only when I have dead band applied and using only 1A to issue bith 1A and 1B. This does not happen if 1A and 1B are inverse of each other but independent without dead band.

Note: I changed the duty cycle to 0.7.

Start ISR code:

    EPwm1Regs.AQCSFRC.all = 0x0000;     // Action-qualifier continuous s/w force register

    asm("  IACK  #0x0001");                // IACK - CLA task 1 force instruction
    asm("  RPT #3 || NOP");                // Wait at least 4 cycles
    while(Cla1Regs.MIRUN.bit.INT1 == 1);   // Loop until task completes

    EPwm2Regs.TBCTL.bit.CTRMODE = 0x0;  // Enable the timer in count up mode
    EPwm1Regs.TBCTL.bit.CTRMODE = 0x0;  // Enable the timer in count up mode

    if (EPwm1Regs.TZFLG.bit.OST == 1)
       asm(" EALLOW");
       EPwm1Regs.TZCLR.bit.OST = 1;
       EPwm1Regs.TZOSTCLR.all = 1;
       asm(" EDIS");

Stop ISR code:

    asm(" EALLOW");
    EPwm1Regs.TZFRC.bit.OST = 1;       // Force Trip PWM1 - force low on output
    asm(" EDIS");
    EPwm1Regs.AQCSFRC.all = 0x0005;     // Force continuous low on output - Action-qualifier continuous s/w force register
    EPwm2Regs.TBCTL.bit.CTRMODE = 0x3;  // Disable the timer
  

    EPwm1Regs.CMPA.bit.CMPA = 0;    // Set duty cycle to 0 to start again
    //EPwm1Regs.CMPB.bit.CMPB = 0;    // Set duty cycle to 0 to start again


    asm(" EALLOW");
    //--- Force Task 8 to clear to zero the controller and duty cycle
        Cla1Regs.MIER.all = 0x0081;            // Enable CLA interrupt 8
        asm("  IACK  #0x0080");                // IACK - CLA task force instruction
        asm("  RPT #3 || NOP");                // Wait at least 4 cycles
        while(Cla1Regs.MIRUN.bit.INT8 == 1);   // Loop until task completes

    //--- Enable CLA Task 1 interrupt and disable Task 8 interrupt
        Cla1Regs.MIER.all = 0x0001;        // Enable CLA interrupt 1 (and disable interrupt 8)

    asm(" EDIS");                      // Disable EALLOW protected register access

Hi Dan,

Dan8 said:

I have managed to remove the 200us from the first start after power on (diagram 1)

What did you change in your initialization to accomplish this?

Also, may I please know what your action qualifier and deadband settings are? 

Best Regards,

Marlyn

I forced CLA task 1 by software in the CLA initialization and another software force of task 1 in the start ISR.

Action qualifier and deadband settings in the PWM initialization:

EPwm1Regs.AQCTLA.all = 0x0012;   

EPwm1Regs.DBCTL.bit.IN_MODE = 00;    // S5 and S4 Pass 1A:0, Pass 1B:1
EPwm1Regs.DBCTL.bit.POLSEL = 10;    // Polarity Select - S2:0 Pass 1A to OutA , S3:1 Pass inverted 1A to OutB
EPwm1Regs.DBCTL.bit.DEDB_MODE = 0;  // DEDB_MODE S8:0 - Pass A1 with RED, S8:1 - Pass A1 with both RED and FED
EPwm1Regs.DBCTL.bit.OUT_MODE = 11;  // S1 and S0 Deadband disabled: 0, Enabled: 1
EPwm1Regs.DBRED = 100;                // Rising Edge Delay = Ttbclk x DBRED
EPwm1Regs.DBFED = 50;                // Falling Edge Delay = Ttbclk x DBFED

Regarding the CLA task software force worked for now because I am using a fixed duty cycle for testing, however I am expecting problems with this in the real implementation because the duty cycle will be controlled by PI controllers within the CLA task. This might give wrong outputs since the ADCs results will not be present at power startup, which are the values the PI contollers will work on.

Hi Dan,

What is the specific trigger event for the ADC? If I am understanding your requirements correctly, you would like the output to remain low until your start ISR which enables the ADC and CLA tasks, but in your case the CLA is taking too long to provide a duty cycle value which in turn causes one of your outputs to remain high. One possible suggestion, depending on what your ADC trigger is, would be to initiate a software ADC trigger during the Start ISR, have the CLA update the duty cycle value and once that value has been calculated, remove the Action-qualifier continuous s/w force. The last part is key I think, you can force your outputs low until the CLA has a value that can be used.

Best Regards,

Marlyn 

Yes you understood correctly. ADCs are triggered by PWM2.

Hi Dan,

I suggest you do a software trigger for the ADC during your start ISR before you enable the epwm time base counter. Once the CLA task completes and you have a duty cycle value you can start the epwm timers. 

Best Regards,

Marlyn

Hi,

I will try this. Is there a way to know that the CLA task is complete and the CLA interrupt routine is ready? since I will be starting the converter from within an ISR.

Hi Dan,

The CLA can interrupt the c28x so the interrupt flag would be one way to tell. Another way would be to check the appropriate bits of the MIRUN register. The bit will be set to 1 while the CLA task is running. If this bit goes from 0 to 1 and back to 0 then you know the CLA tasks was initiated and completed. 

Best Regards,

Marlyn

I am trying to do something as suggested, however I am still getting the high period after restart. It is strange that it happens only when applying the dead band.

Dan,

If you setup a compare value within your start ISR, before you clear the trip zone flag, do you still see the high period after restart?

Best Regards,

Marlyn

Hi,

Tried this, still with the high period.

Dan would you mind toggling a GPIO signal or setting it to high once you disable the trip zone signal and at other key points within your program? I want to understand, if possible, when certain events are taking place and when that is affecting your output.

Best Regards,

Marlyn

I will try and get back.