Hi,
I am using the C28 as a SPI Slave. I am using two DMA Channels to load and remove data from the SPIA Tx and RX FIFOs. If the C28 code starts running while the Chip Select is not active, everything works fine. The DMA and SPI transfer line up and all the expected data is transmitted to to the SPI Master. At the end of a SPI transfer there is no data left in the SPI fifos.
However, if the SPI DMA is started in the middle of a transfer or interrupted (think c28 breakpoint or partial transfer from the host) then the DMA and SPI Transfers do not align. I can identify this by looking at the state fo the DMA transfer when the SPI CS goes high.
I would like to reset the DMA and SPI bus when I detect this mismatch. I know how to reset the SPI FIFO and DMA transfer, but it appears that all the subsequent transfers are shifted by 16 bits. My current theory is that when the SPI Rx and Tx FIFOS are cleared, they don't reset the data in the SPIDAT register. I've validated this to some extent by writing the SPIDAT register before I start the DMA transfer. So when the next transfer starts, data is shifted from the spidat and then from the fifos. The first byte I want sent is really sent as byte two.
Is there a way to clear the SPIDAT register such that DMA transfers to the FIFO address will automatically drop through? Do I need to fully reset the SPI hardware?
Thanks,
-Colin
