Hi, I plan to use both EMIF1(32-bit) and EMIF2(16-bit) which are connected with FPGA.
Our system can access like below. Could you let me know if below usages is possible ?
1) CPU1 software access EMIF1 and EMIF2 to read/write FPGA.
2) CPU2 software access EMIF1 to read/write FPGA.
Best regards,
Hidehiko