TMS320F28375D: Flash Kernel Problems

Amarjit Singh

I have been using the flash-kernel (default files) to program the device. However, when I do DFU1 it gives me the following error:-
SUCCESS of Command
ERROR Status: VERIFY_ERROR
ERROR Address: 0x80000

Even though the application load is successful.

But, when I DFU2, it fails with the following error:-

Checksum does not match... Please press Ctrl-C to abort.

This is coming from the following code:-

void loadProgram_checksum(FILE *fh)

....

//Send ACK as expected
WriteFile(file, (unsigned char*)&ack, 1, &dwWritten, NULL);

rcvData = (sendData[1] << 8) + sendData[0];

//Ensure checksum matches
if (checksum != rcvData)
{
printf("\nChecksum does not match... Please press Ctrl-C to abort.");
while (1){}
}

while (fileStatus == 1)
{
unsigned int blockSize;

This happens all the time. This works with the blinky apps and our older .hex files. However, it fails consistently with our newer hex files. I have attached the linker files. I can send the .map files as well.

Please let me know if any additional information is required.

CPU1

MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */

PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */

PAGE 1 :

BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800

RAMLS5 : origin = 0x00A800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x00B000
RAMGS12131415 : origin = 0x018000, length = 0x003FF8 // For cpu2
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */

CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400

}

SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(8)
.text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
codestart : > BEGIN PAGE = 0, ALIGN(8)
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.switch : > FLASHB PAGE = 0, ALIGN(8)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

#if defined(__TI_EABI__)
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS3, PAGE = 0 ALIGN(8)
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS5, PAGE = 1
.sysmem : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASHF, PAGE = 0, ALIGN(8)
#else
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
.ebss : > RAMLS5, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
.cio : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHF PAGE = 0, ALIGN(8)
#endif

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif

#endif

/*** User Defined Sections ***/
FWVERSION_MEM : > RAMGS0, PAGE = 1
CONFIG_AIM_MEM : > RAMGS0, PAGE = 1
CALIBRATION_AIM_MEM : > RAMGS0, PAGE = 1
ACK_MSG_CONFIG_MEM : > RAMGS0, PAGE = 1
ACK_MSG_CALIBRATION_MEM : > RAMGS0, PAGE = 1

RMS_HALF_MEM : > RAMGS1, PAGE = 1
EVENTS_FIFO_BUFFER_MEM : > RAMGS1, PAGE = 1
TRENDS_FIFO_BUFFER_MEM : > RAMGS1, PAGE = 1
BUFFERS_MEM : > RAMGS1, PAGE = 1

/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

CPU2

MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000080, length = 0x000380
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002

PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800

RAMLS5 : origin = 0x00A800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x00B000
RAMGS12131415 : origin = 0x018000, length = 0x003FF8 // For cpu2
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */

CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}

#endif

/*** User Defined Sections ***/
COMM_RX_BUFFER_MEM : > CPU2TOCPU1RAM, PAGE = 1
SDP_CONTEXT_MEM : > RAMGS12131415, PAGE = 1

/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

over 5 years ago

0 Sira Rao80 over 5 years ago

TI__Mastermind 27675 points

I have assigned this issue to a colleague who will reply. Thanks, Sira

0 Anu Biradar over 5 years ago

TI__Expert 5630 points

Hello,

Here are a couple of things to check:

Do any portions of your newer hex files overlap with the kernel in Flash?

Are you using the same post build step or the same parameters in the hex utility tool that you do with your older hex files?

Thanks,

Anu

0 Amarjit Singh over 5 years ago in reply to Anu Biradar

Prodigy 20 points

The problem was with the line endings in the .hex files. For some reason, it worked fine with the Linux line endings last time. But with our new hex files, it didn't work. So, we converted the hex files using unix2dos. It worked fine after that. It would have been nice if this type of information was included in the readme file.

0 Anu Biradar over 5 years ago in reply to Amarjit Singh

TI__Expert 5630 points

Hello,

Thanks for the feedback. Were you using the same command to create both hex files? This will help in figuring out the information to put in a readme.

Thanks,

Anu

0 Amarjit Singh over 5 years ago in reply to Anu Biradar

Prodigy 20 points

Yes. Please note that we build our project in Linux which creates the .hex files with the Linux line endings. But again, our older files worked fine before. In fact, one of the newer files worked fine too (CPU1) but it was giving the verify error even though it programmed it correctly.

0 Anu Biradar over 5 years ago in reply to Amarjit Singh

TI__Expert 5630 points

I'll reach out to a compiler expert to find out if there were changes in the hex utility tool that caused a difference.

Thanks,

Anu

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TMS320F28375D: Flash Kernel Problems