• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 83 subscribers
  • Views 792 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280025: CMPSS - Trip Zone Questions

Jens G
Expert 3335 points
Part Number: TMS320F280025


Dear C2000 group, 

please could you take a look into the questions regarding the CMPSS and the clock tree.

1 . How long takes the clock-fail-detection with external oscillator and PLL? Please provide the answer in clock cycles. 

2. How do the synchronous latches in CMPSS, PWM and output x-bar behave during this time? I assume that the PLL would have to run a little bit without an external oscillator, wouldn't it?

3. How does the DAC on the comparator during this time?

4. Can the comparator event be latched asynchronous?

5. Can be the clock fail signal used to set the GPIO (somehow)?

6. SW methods to ensure the correct state of the configuration registers at runtime?

Thanks for your help and best regards

Jens 

  • 0
    TI__Mastermind 28275 points

    Hi Jens,

    Need clarifications on some of your questions. Responses below:

    1. Is this in reference to the MCD or DCC?

    2. Latch output state will be unaffected unless explicitly cleared. Yes, the PLL will run a bit until the system switches to INTOSC1 automatically.

    3. The compdac will maintain it's state unless changed.

    4. The comparator component in the CMPSS is analog and clocks have no effect on it so yes, the async output will still work.

    5. Missing clock is an NMI condition so the errorsts pin will be activated.

    6. I don't understand this question. Can you explain?

  • 0 in reply to Frank Ankapong
    Prodigy 20 points

    Hi Frank,

    Jens was so kind to ask these questions on my behalf, so I will carry on. Thank you very much for your input so far.

    The general use case is to have a fast, safe and latched shutdown of PWM and of one GPIO for a regular one shot trip and also for hardware failures like external clock failure or ECC. This should happen without software intervention.

    1. It seems that DCC can't raise a trip event. The datasheet states that MCD will take at max 0.8 ms before clockfail will be raised. PLL Reference Clock Lost Detection will react in 1 us (10*OSCCLK), right? So my assumption is, that the reaction time of the PWM trip is 1 us after external clock loss.

    2. I think about it the other way round. Are the latches able to catch and hold a possible comparator event, while the PLL is in limp-mode or the clockfail is not yet risen? Will there always be some clock signal available for the synchronous latches? (PLL limb, glitch free clock switch, ...)?

    3. Thanks

    4. In CMPSS, EPWM and output x-bar there seems to be only synchronous latches available which need a clock. The async path is not able to latch anything.

    5. According to Figure 17-50 it seems possible to have trips for clockfail and ECC. These trips seem also to be routable through the DC to force the GPIO low, which also reacts on the regular one shot trip event. Like this, one single GPIO would go low on either event types: regular one shot and also hardware failure type. Is this correct?

    6. Off-topic, please ignore.

  • 0 in reply to Daniel Stöckner
    TI__Mastermind 28275 points

    Hi Daniel,

    Responses below:

    1. That is correct, DCC can't raise a trip event but it is possible to configure it to have a faster reaction time compared to MCD. You will need to implement some of the DCC actions in software. The MCD has a slower reaction time but it's actions all happen in hardware without software intervention. Same goes for PLL Reference Clock Loss which has a faster detection time compared to MCD like you pointed out. However, neither can detect frequency drift like the DCC can.

    2. Yes, if the PLL is enabled, there will always be a clock to the system even in limp mode.

    4. Are you asking about the latch in the CMPSS? The EPWM xbar does not have a latch but the output xbar does.

    5. Yes.

    By the way, you can simulate all the above in case you wanted verify your design. If you are using a XTAL, just turn it off in the code and see how the system behaves. You can also power down INTOSC2 if you are using that as the system clock

  • 0 in reply to Frank Ankapong
    Prodigy 20 points

    4. I was talking about the OSHT latch in TripZone submodule. But because of the clock always being available, it doesn't matter anymore if the latches are synchronuous or not. Thanks.

    5. According to table 9-4 it is not possible to combine clockfail and comparator event to a single GPIO. My workaround would be to use a currently unused PWM module for outputting a constant high signal. The PWM trip zone would be configured to set the channel low on clockfail trip or comparator event. Is there a better way? I'm asking, because the currently unused PWM module might be needed for a different purpose in the future.

    Thanks for your fault injection hint. Will try at the next opportunity.


  • 0 in reply to Daniel Stöckner
    TI__Mastermind 28275 points

    Hi Daniel,

    5. That is correct. CLOCKFAIL only goes to the NMI and EPWM. If you don't want to use the EPWM, an alternative is utilize the Errorsts pin which will activate on a CLOCKFAIL. You can then use the Input Xbar to tap off the Errorsts and OR it with the comparator trip event in the output xbar.

    Let us know if you have any more questions.