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LAUNCHXL-F28379D: EPWM Frequency Calculation

Jin Gao1
Prodigy 90 points
Part Number: LAUNCHXL-F28379D

Hello,

This may seem pretty straight forward, but when I was running the epwm_up_aq example the frequency I am measuring on the scope is different than what I expected.

for an up count mode Fpwm = 1/Tpwm, and Tpwm = (TBPRD + 1) x T_TBCLK. The example code has TBPRD for 2000, and I assume the epwm clock is at 100 MHz, then Fpwm should be 50kHz, but I am measuring 6.25 kHz.  The only thing I can think of is the 100 Mhz assumption is wrong, where can I check on this or modify it?

Thank you

Jin

  • +1
    TI__Mastermind 24800 points

    Hi Jin,

    Here is why you are measuring 6.25 kHz:

    Tpwm = (TBPRD + 1) x T_TBCLK

    TBPRD is 2000

    TBCLK = EPWMCLK/ (HSPCLKDIV * CLKDIV)

    Looking at the example we see that both HSPCLKDIV and CLKDIV are set to divide by two.

    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; 
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    To find the value of EPWMCLK, you can refer to the EPWMCLKDIV bit of the PERCLKDIVSEL register. This is the EPWM Clock Divide Select bit. By default it is set to a divide by two of PLLSYSCLK.

    Now, to find PLLSYSCLK,

    If you open the declaration for the InitSysCtrl() function within the example you'll find where PLLSYSCLK is getting set:

        InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2);

    XTAL_OSC is 10MHz on the launchpad (this can be found looking at the BOM/schematic for the launchpad)

    The calculation is as follows: fPLLSYSCLK = fOSCCLK * (SYSPLLMULT.IMULT + SYSPLLMULT.FMULT) / SYSCLKDIVSEL.PLLSYSCLKDIV

    Putting in values passed in to InitSysPll we get fPLLSYSCLK = (10M) * (20) /2 = 100MHz

    Because EPWMCLKDIV is set to divide by two, EPWMCLK = 100M /2 = 50MHz

    Plugging EPWMCLK back into out TBCLK calculation: 50M / (4) = 12.5M

    So, Tpwm = (2001) / (12.5M) = 0.00016

    Fpwm = 1/Tpwm = 1/0.00016 = 6.246 kHz

    If you want the EPWM clock to be at 100MHz then the easiest way is to change the EPWMCLKDIV to a divide by 1. This can be done by including the following code in your program: 

        EALLOW;
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
    EDIS;

    For a 50kHz output (Fpwm) there are many ways to accomplish this. If you change the EPWM clock to 100MHz then you can adjust the TBPRD accordingly, setting it to 500 should give you a 50kHz output.

    Best Regards,

    Marlyn