TMS320F280049C: ADC Sampling

Hi Jan,

I guess there are a couple things to untangle/address here. 

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First: burst mode.  This doesn't make the ADC sample any faster, but instead allows a single global trigger to cause a burst of conversions.  For example, if ePWM3A is the burst trigger and the burst size is 4, each time ePWM3A trigger is received, the next 4 SOCs will convert.  In the case of all round-robin SOCs, the first trigger will cause SOC0-SOC3 to convert, the next trigger will cause SOC4-SOC7 to convert, ... etc.  This can provide two main benefits: buffering of the ADC results past just the last conversion, and undersampling of some signals (both of which may be helpful for you).

Consider the following setup:

• ADC-A + B: burst mode, all SOCs round-robin (no high priority SOCs), burst size = 2, burst trigger = 200kHz ePWM
• SOC0, 2, 4, ... 14 = channel A0 or B0
• SOC1 = A1 / B1 
• SOC3 = A2 / B2
• SOC5, 7, 9, ... 15 = dummy channel
• ADC ISR triggered by ADC-A SOC15 

The ISR will get triggered after 8 ePWM triggers.  RESULT14 for ADC-A and ADC-B will have the latest A0/B0 result and RESULT 12 will have t-1 A0/BO result ... to RESULT0 which has the t - 7 A0/B0 results.  The effective sampling rate for A0/B0 is 200kHz and the ISR rate is 200kHz / 8 = 25kHz.  Samples are equidistant. 

Each ISR will also generate 1 new result for A1 / B1 / A2 / B2 so the sampling rate for these channels is 25kHz (undersampled relative to the trigger frequency)

Note: Maybe a better strategy for your specific case would be to use ADC-C for the non-simultaneous samples, with all ADCs in burst mode with burst size = 1.  This would allow 16 A0/B0 results to be processed per ISR and under sampling of up to /16 on the other channels, which gets you to the ~12kHz rate you need. 

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Second: DMA

Definitely use the DMA if you are trying to build up a longer record or A0/B0 without taking a control action on every new A0/B0 sample.   You can use this with or without burst mode with the DMA being triggered the same way as the ISR (from the ADCINT).  In the burst mode case, you can trigger both the DMA and an ISR (perhaps the ISR processes the misc. conversions but the DMA is allowed to build up a record of A0/B0 conversions).

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Third: async. triggering

One important thing to keep in mind is that if your slower ePWM triggers are asynchronous to the ~200kHz ePWM, you may not be able to get equally spaced samples if the samples share an ADC.  This is because even in the case of 'high priority' SOCs the ADC will not abandon an in-process conversion, so if your slower loop has an ADC conversion in progress, the faster loop's conversions may still be delayed.

• The PPB delay capture feature can actually be used to determine if and how long (in cycles) a conversion was delayed, if that is helpful
• The maximum delay in this case would also be approximately the time for 1 ADC conversion, if that is tolerable

The other alternative would be to allocate your async. conversions to a single ADC (say ADC-C).  This unfortunately isn't recommended/supported on this device because the async. ADCs will cause interference with each other, resulting in poor analog performance. 

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Overall, can the 3 ADC burst mode situation work for you? Or do your slower ePWM based conversions occur asynchronously or with variable timings relative to the faster ePWM?    

Hello Devin,

thanks a lot for the input. To be honest, this is my first TI device, so I need to ask some further question:

Is in burst mode the priority always removed? Or do I need to call further routines than ADC_enableBurstMode .

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To your note: ADC C cannot be configured to use a EPWM if I got the documentation right. But they should also be triggered by an epwm. I could possibly free one timer, but actually they are currently in use. 

In general we will do a redesign and my hardware said I can choose free which signal are going to be on which ADC.

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Is there any example to use DMA and burst mode together, or is it simply to setup the config and use DMA_TRIGGER_ADCA0 here?

  DMA_configMode(DMA_CH1_BASE, DMA_TRIGGER_ADCA0,
(DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_DISABLE |
DMA_CFG_SIZE_32BIT));

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Third: async. triggering

 What do you mean with asynchronous to 200 ksp.

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Your Questions:

Overall, can the 3 ADC burst mode situation work for you? Or do your slower ePWM based conversions occur asynchronously or with variable timings relative to the faster ePWM?    

The slower ePWM based signals are just average filtered to reduce noise. In this context, I think it is ok, if the samples are not totally equidistant. So the less frequent signals are influenced by the A0/B0, but do not depend on them. Furthermore, I just need to process them let’s say every 100 or 500 ms and I only look at the samples measured during the last A0/B0 periode (one sinus wave of A0/B0 2.5 ms).

Currently I just use a ISR for every signal, so when processing the signal, I just can stop the EPWM from triggering. If I could move the other signals to ADCC I could just stop the epwm and I do not need to implement a dual head buffer saving memory, but like I asked, ADC cannot use EPWM right? 

The high sampled signals also should be processed by the CLA, here a DMA could be used to directly move the data to the CLA shared mem?

Thanks in advance.

Jan

Thanks for the detailed answer. This sorted things out.