TMS320F28388D: Connection problems with the debugger

Hi Jan,

When you press Startbutton, how does the code terminate? Do you have any breakpoint at the end?

Best Regards,

Nirav

Hi Nirav,

Thank you for your questions.

when i have loaded the programm and i am pressing the startbutton sometimes i get the error and nothing is working. I have lost the connection to the DSP. When i press the terminate button i get back to "CCS Edit". 

I have no breakpoint in the Code.

Here is the report of the "console" of CCS after i pressed the bug  "debug  (name of project)" button in Slide "CCS Edit"  and the error occured after pressing the "Resume" button is the "CCS debug" slide.

28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
CM is out of reset and configured to wait boot.
(If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
CM is out of reset and configured to wait boot.
(If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
CM is out of reset and configured to wait boot.
(If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: Error: (Error -1044 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 9.2.1.00046)

C28xx_CPU1: Trouble Halting Target CPU: (Error -1135 @ 0x16A4E) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 9.2.1.00046)
C28xx_CPU1: Unable to determine target status after 20 attempts
C28xx_CPU1: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging

best regards

Jan Hummel

The Dissassmbly is pointing to the start of the Main function when the Error occures

Hi Jan Hummel,

Can you step through the code and see when it looses connection?

Best Regards,

Nirav

Hi Nirav,

I can step in the code.

the Error occurs somewhere in the InitSysCtrl(); but i cant locate the exact code which triggers the error. 

It’s hard to find it because the Error occurs only sometimes.

when the Error occurs the reset line XRS on Pin F19 is forced low. I think a POR occurs because the RAM is empty. I can’t read out the POR flag in reset register because the boot-rom delete it.

I will try to find more Information next week.

 Best Regards 

Jan

Hi Jan,

Can you step into the InitSysCtrl() to locate where exactly the error occurs? Are you using the latest C2000Ware version?

Best Regards,

Nirav