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TMS320F28379D: CLB Counter Load Question

Ed Sanders
Genius 4085 points
Part Number: TMS320F28379D


Greetings,

 I have a CLB design where I need to have a counter come out of the CLB reset condition, using GLOBAL_EN <- 1, with a count register value which is non-zero so that the zero output stays low.  To do this, I set the event input to 1, told it to Load, and gave it a non-zero event_load_val value.  When I set the GLOBAL_EN, I was expecting the zero output to pulse high for a clock and then go low.  But instead, happily, it was simply low.  Is this the expected behavior?  If so, why?

Thank you,

Ed

  • +1
    TI__Guru 52040 points

    I believe that is the case because of the priority of the LOAD event. You can always check this with the System C simulation models. They were written by design so they have been accurate every time I used them. If the Event load action is high, it should imediately take affect after you enable the CLB.

    Nima