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TMS320F28069: Problems of modifying cmd file

Part Number: TMS320F28069


Hello, I'm currently working on a project with the dsp of 28069. As the project grows, the code amound becomes larger and larger. Recently, the compiler tells me that

"../28069_RAM_lnk.cmd", line 121: error #10099-D: program will not fit into
   available memory.  placement with alignment/blocking fails for section
   ".text" size 0x34e5 page 0.  Available memory ranges:
   RAML0_L3     size: 0x2000       unused: 0x2000       max hole: 0x2000    
   .text            : > RAML0_L3,   PAGE = 0

I think maybe I can enlarge .text by my self. Then, I tried to enlarge the .text field by increasing the size of RAML0_L3 from 0x002000 to 0x004000. This enlarged area overlaps with RAML4 and RAML4 is occupied by .ebss and so on, so I changed their location to RAML5. Since RAML5 is occupied by "DMARAML5", I also changed DMARAML5's location to RAML6. The below is my whole cmd file

/*
// TI File $Revision: /main/3 $
// Checkin $Date: March 3, 2011   13:45:43 $
//###########################################################################
//
// FILE:    28069_RAM_lnk.cmd
//
// TITLE:   Linker Command File For F28069 examples that run out of RAM
//
//          This ONLY includes all SARAM blocks on the F28069 device.
//          This does not include flash or OTP.
//
//          Keep in mind that L0,L1,L2,L3 and L4 are protected by the code
//          security module.
//
//          What this means is in most cases you will want to move to
//          another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: $ 
// $Release Date: $ 
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN       : origin = 0x000000, length = 0x000002
   RAMM0       : origin = 0x000050, length = 0x0003B0
   RAML0_L3    : origin = 0x008000, length = 0x004000	 /* RAML0-3 combined for size of .text */
   														 /* in Example_F2806xSWPrioritezedInterrupts */
   RESET       : origin = 0x3FFFC0, length = 0x000002
   FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	 /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50    /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C    /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */

   BOOTROM    : origin = 0x3FF3B0, length = 0x000C10


PAGE 1 :

   BOOT_RSVD   : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */
}


SECTIONS
{
   /* Setup for "boot to SARAM" mode:
      The codestart section (found in DSP28_CodeStartBranch.asm)
      re-directs execution to the start of user code.  */
   codestart        : > BEGIN,      PAGE = 0

#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAMM0,      PAGE = 0
   #else
   ramfuncs         : > RAMM0,      PAGE = 0   
   #endif
#endif
   
   .text            : > RAML0_L3,   PAGE = 0
   .cinit           : > RAMM0,      PAGE = 0
   .pinit           : > RAMM0,      PAGE = 0
   .switch          : > RAMM0,      PAGE = 0
   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,      PAGE = 1
   .ebss            : > RAML5,      PAGE = 1
   .econst          : > RAML5,      PAGE = 1
   .esysmem         : > RAML5,      PAGE = 1

   IQmath           : > RAML0_L3,   PAGE = 0
   IQmathTables     : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

   DMARAML5	        : > RAML6,      PAGE = 1
   DMARAML6	        : > RAML6,      PAGE = 1
   DMARAML7	        : > RAML7,      PAGE = 1
   DMARAML8	        : > RAML8,      PAGE = 1

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

After this, I compiled, everyting seemed fine, not bug, no warning. But when I ran this code on my board, I can see from the "Expressions" window that all of my variables are changing randomly. It seems that the code has been out of control.

I have read the memory map from the datasheet, L0 to L3 seems different from L4, L0 to L3 are DPSARAM while L4 is SARAM. Is it due to this difference and .text should never use L4 ?

Can anyone explain this to me? I'll sincerely appreciate your help!

  • Thanks for reaching out to the TI E2E forums.

    I found a small error in the .cmd you attached above, at line 138/139 you've allocated both DMARAML5 and DMARAML6 to the same physical memory space. Since L5 is now allocated to your .ebss/.econst we definitely don't want the DMARAML5 mapped there, I'd just delete that line of code or you could break RAML6 into smaller chunks if you need separate allocations for the DMA.

       DMARAML5	        : > RAML6,      PAGE = 1
       DMARAML6	        : > RAML6,      PAGE = 1

    In terms of functionality for code or data, all the Lx RAMs are identical in performance.  The DPSRAM is Dual Port, since they are shared between the CPU and either the CLA(L0-L3) or the DMA(L5-L8).  If you are not using either, then there will be no performance penalty to your C28x data or program.  There is a init process for the CLA, so I don't believe you've accidentally activated it.  If you are using the DMA, we may want to check

    Finally, even though we've allocated specific RAMs for the DMA, the DMA itself is not automatically blocked from any address it has access to.  So even though L5 is not allocated to DMA in the linker, if you've programmed it to write to those address in L5 there's nothing that could stop it from doing do.  Esp if you were using L5 previously for the DMA I'd have a look at the DMA initialization code to make sure its not still pointing to L5 either in an active or a shadow register load/reload.

    Let me know what you find and if I can be of more help.

    Best,

    Matthew

  •   Esp

    Thank you for your timely reply. I have deleted the line for the allocation of DMARAML5 as you mentioned. But the problem is still the same. Now my cmd file looks like as below

    MEMORY
    {
    PAGE 0 :
       /* BEGIN is used for the "boot to SARAM" bootloader mode   */
    
       BEGIN       : origin = 0x000000, length = 0x000002
       RAMM0       : origin = 0x000050, length = 0x0003B0
       RAML0_L3    : origin = 0x008000, length = 0x004000	 /* RAML0-3 combined for size of .text */
       														 /* in Example_F2806xSWPrioritezedInterrupts */
       RESET       : origin = 0x3FFFC0, length = 0x000002
       FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	 /* FPU Tables in Boot ROM */
       IQTABLES    : origin = 0x3FDF00, length = 0x000B50    /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FEA50, length = 0x00008C    /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */
    
       BOOTROM    : origin = 0x3FF3B0, length = 0x000C10
    
    
    PAGE 1 :
    
       BOOT_RSVD   : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */
       RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
       RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
       RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
       RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
       RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
       USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */
    }
    
    
    SECTIONS
    {
       /* Setup for "boot to SARAM" mode:
          The codestart section (found in DSP28_CodeStartBranch.asm)
          re-directs execution to the start of user code.  */
       codestart        : > BEGIN,      PAGE = 0
    
       ramfuncs         : > RAMM0,      PAGE = 0
       .text            : > RAML0_L3,   PAGE = 0
       .cinit           : > RAMM0,      PAGE = 0
       .pinit           : > RAMM0,      PAGE = 0
       .switch          : > RAMM0,      PAGE = 0
       .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
    
       .stack           : > RAMM1,      PAGE = 1
       .ebss            : > RAML5,      PAGE = 1
       .econst          : > RAML5,      PAGE = 1
       .esysmem         : > RAML5,      PAGE = 1
    
       IQmath           : > RAML0_L3,   PAGE = 0
       IQmathTables     : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
    
       /* Allocate FPU math areas: */
       FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
    
       DMARAML6	        : > RAML6,      PAGE = 1
       DMARAML7	        : > RAML7,      PAGE = 1
       DMARAML8	        : > RAML8,      PAGE = 1
    
    }
    

    Besides, I am not using DMA in my project. Maybe I have initialized the clock for DMA, but absolutely I did not write any code for DMA.

    Addition clues have been found. After I ran my code, all of the variables just changes randomly and when pause it, it shows "Break at address "0x89" with no debug information available, or outside of program code." as follows. I think the code has already gone out of control.

    When I switch to the default cmd for flash mode, the code works fine, which proves that there is no mistake about my code.

    In a word, the cmd for RAM is still not working, can you give me addtional help?

  • I have found new clues.

    I tried to run my code line by line and found that whenever the program ran into the third line of this function below, it would crash.

    void send_data(char screen,const char control_id[2],float freq,char* format){
        char *result;
    
        result = malloc(40);
        sprintf(result,format,freq);
    
        scia_send_char(send_begin, 3);
        if(screen == 0){
            scia_send_char(screen_id0, 2);
        }else{
            scia_send_char(screen_id1, 2);
        }
        scia_send_char((char *)control_id, 2);
        scia_msg(result);
        scia_xmit('\0');
        scia_send_char(send_end, 4);
        free(result);
    }

    I guess maybe it is the problem for the variable "result". I checked the address of it and found that it is inside ".stack" area, which is mapped to M1 SARAM.

       .stack           : > RAMM1,      PAGE = 1
     

    I tried to re-map .stack to another place, which is L6 and then it works, the code works perfectly.

    Though I have solved this, I am totally confused and I still don't know why. Looking forward to your replay!

  • Glad that you are able to continue to debug/develop the code.  Are you copying any sections from Flash to RAM to speed up the execution?  You would see the memcpy() function in your code. 

    Looking at the linker, there is nothing intentional being allocated to M1 other than the stack.  I will add the M0/M1 are contiguous, so if M0 were larger than we thought it could over-write M1.  The linker should have thrown an error if M0 sections were in excess of what you have allocated, unless the pinit or cinit is dynamic.

    If you look in the debug directory there should be a .map file generated, if you could look through this with the old linker it would show if there is some of M1 space somehow allocated. 

    Right now I'm thinking the memcpy is the most obvious reason.

    Best,

    Matthew

  • Hi, MathewPate, thank you for your reply.

    Actually, I did not use memcpy() to copy any sections from FLASH to RAM. However, inspired by your suggestion, I tried to see the address of result, which is allocated dynamically in the function below. When the old linker is adopted, I found that the address for result is allocated to "0x00000408", which is inside M1 section.

    void send_data(char screen,const char control_id[2],float freq,char* format){
        char *result;
    
        result = malloc(40);
        sprintf(result,format,freq);
    
        scia_send_char(send_begin, 3);
        if(screen == 0){
            scia_send_char(screen_id0, 2);
        }else{
            scia_send_char(screen_id1, 2);
        }
        scia_send_char((char *)control_id, 2);
        scia_msg(result);
        scia_xmit('\0');
        scia_send_char(send_end, 4);
        free(result);
    }

    Since 0x00000408 is inside ".stack", I think maybe there is something wrong because as far as I know, dynamically allocated memory should be in heap. So is it due to this that causes the code to crash?

    According to the information in "SPRU514", which is the compiler user's guide, the dynamically allocated memory should be inside ".sysmem" section. However, ".sysmem" is not defined in my linker, so, should I try to define ".sysmem" to a certain place to solve this problem?

  • According to the information in "SPRU514", which is the compiler user's guide, the dynamically allocated memory should be inside ".sysmem" section

    The ".sysmem" section in used for EABI, and ".esysmem" is used for COFF.

    In the CCS project properties under CCS General -> Project is Output Format is set to "legacy COFF" or "eabi (ELF)"?

    Some of the C2000 example linker command files only have the sections for COFF, and if the project is changed to be EABI the EABI section names need to be added to the linker command file. E.g. If you get warnings such as the following:

    warning #10440-D: creating output section ".sysmem" without a SECTIONS specification. For additional information on this section, please see the 'C2000 Migration from COFF to EABI' guide at https://software-dl.ti.com/ccs/esd/documents/C2000_c28x_migration_from_coff_to_eabi.html

  • Hi,Gillon. Thanks for answering. Currently, the output format is legacy COFF.
    But about the problem I faced, do you have any idea?
    thank you

  • Since 0x00000408 is inside ".stack", I think maybe there is something wrong because as far as I know, dynamically allocated memory should be in heap.

    Do you mean the address of the result variable, or what the address which result points to?

    The following is an example which worked using COFF:

    And the linker map contains:

    .stack     1    00000050    00000300     UNINITIALIZED
                      00000050    00000300     --HOLE--
    
    .esysmem   1    00008c00    00000400     UNINITIALIZED
                      00008c00    00000004     rts2800_fpu32.lib : memory.c.obj (.esysmem)
                      00008c04    000003fc     --HOLE--

    The the result variable is located at address 0x00000058 which is on the stack.

    Whereas result points at address 0x00008C02 which has been allocated from the heap.

  • Hi, Gillon. Thanks for your timely reply. Yep, you are right and I made a mistake before. The allocated address is actually inside the heap, and the pointer is inside the stack, which is in accordance with my experiment result.

    I think I have targeted the problem, which is due to the "sprintf" instead of the dynamic memory allocation. I have found that other people met the same problem in "">e2e.ti.com/.../tms320f28069m-printf-issues-and-stack-overflow". 

    They suggested to increase the size of stack because maybe sprintf needs larger stack memory than 0x400, which is the size for .stack in the default linker file. So I changed the stack size from the compiler setting and increased it to 0x800. Besides, since .stack is mapped to M1 by default, which only has the size of 0x400, I re-mapped the .stack to RAML6. And then, the problem solved.

    Thanks anyway for your help! Thank you guys.