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TMS320F280049C: 280049 ADC sample question

Foriner
Intellectual 425 points
Part Number: TMS320F280049C

now i test ADC sample on 280049,  use external ref of 3.184V. when i connected the ADC sample pin to GND ,the sample value is 0 , that's right

but when i connected the ADC sample pin to VREFHI pin of DSP,  the sample resault is only 4027, not 4096 ,What factors contribute to this phenomenon? is this normal?

  • 0 in reply to Joseph Casuga
    TI__Mastermind 37790 points

    That could be caused by a couple of factors:

    1.) Can you see what other components or connections (RC network or other circuits) there are in the ADC sample pin where VREFHI is connected?  If there is a network connected to the sample channel, it could be that the signal gets into a voltage divider where in the sample channel actually gets less than the value of VREFHI

    2.) Can you confirm what pin you are using as the sample channel and ensure that this is not one of the DAC signals (VDAC, DACOUT..etc)?  If DAC is active and the ADC sample channel you are using is one of the DAC muxes, then the input signal may be contending with DAC signals.

    It would help debug the issue if you can provide more details about the circuit.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Intellectual 425 points

    perfect answer, And the reason is that there's a RC filter at the AD port, R=2K C=0.1uF;

    Why does RC matter so much? I'm just sampling a DC signal(VREFHI)

    What is the internal resistance of the ADC port?

  • 0 in reply to Foriner
    TI__Mastermind 37790 points

    Please refer to the datasheet section under ADC Input Model (7.10.1.2.3).  It has a table containing the associated sampling capacitance, mux resistance and parasitic capacitance per pin.  There is also another important part in the TRM section under Choosing an Acquisition Window Duration in the ADC chapter (13.15.2).  This section in the TRM gives a good illustration on how the overall circuit impedances affect conversion, specifically the sampling time (SH).

    Using the RC values you have provided, I have calculated that the sampling time required for a 1/4LSB settling error is ~140uS.  The SH register, ACQPS can only hold a max value of (511+1) * SYSCLK period.  In the F280049 device, the max SYSCLK is 100MHz (10nS) so the max sampling time for the ADC is 5.12uS.  You can increase the ACQPS to the maximum value but that will not be enough acquisition time to sample the input signal accurately.  This is the reason why you do not see the full conversion.

    There are two things you can do to remedy this:

         - Lower the external impedances (RC) and using the example case in the TRM to assure that you will have the appropriate SH

         - If you absolutely need the RC (maybe for filtering), you would have to include a buffer (unity gain) after the RC network before feeding the signal to the ADC input,

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Intellectual 425 points

    Thank you very much for your detailed answer， but sorry  i cann't find 13.15.2  the TRM only has 13.14 chapter,  and i also cann't find 7.10.1.2.3 in datasheet of 280049, i download the newest page.  can you help me?

    since in our project all AC sample signal or DC sample signal (voltage or current)have RC filter, So does that mean that the sampling bias of these signals is larger?

  • +1 in reply to Foriner
    TI__Mastermind 37790 points

    Sorry, i might have referred to an old copy of the TRM and datasheet.  Please download the latest copies of TRM and datasheet in ti.com.  In the latest copies of the documents, please refer to TRM section 13.13.2 (Choosing an Acquisition Window Duration) and on datasheet section 7.10.1.2.3 (ADC Input Model) for the values and examples that I was referring to.

    Essentially, yes.  Likewise the external RC network that you mentioned acts as a low pass filter and the ADC input network itself, based from the ADC Input model is also acts as another low pass filter and combinations of these networks and impedances will affect the settling time of the sampling capacitor of the ADC and we have no control over this since this is the behavior of an RC network.  I think your best option will be to add an op amp buffer AFTER the 2K/0.1uF RC network before feeding this to the ADC.  What the op amp buffer will do is isolate the external RC from the ADC input as well as increase the drive strength of the signal to the ADC.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Intellectual 425 points

    thank you for your professional answer, even though add an op amp buffer is a cost add method we may not used.  so this is why we add a calibration to both sample.

    through our discussion ,i have knowed why there was such a large sampling error.

    thank you !

    i suggest in 280049 you TI can disign the PGA have an unity gain select (but now the minimum gain is 3)