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TMS320F280025: How F28002x/4x I2C module handles ACK?

Part Number: TMS320F280025

Dear Champs

I am asking this for our customer. 

1) After getting 8-I2C-clock-cycle I2C data/command, does the I2C module sends ACK first and then enter an ISR?

 

2) Can the I2C module get the 8-I2C-clock-cycle I2C data/command first and enter an ISR and make decision to send ACK or NACK later? That is, use SW-based ACK/NACK?

Wayne Huang

  • Wayne,

    1) After getting 8-I2C-clock-cycle I2C data/command, does the I2C module sends ACK first and then enter an ISR?

    I2CMDR.NACKMOD bit controls whether a ACK bit (or) NACK bit is generated.

    In Slave RX mode:

    When I2CMDR.NACKMOD = 0, I2C module will automatically send ACK bit during acknowledge cycle and then enter ISR.

    When I2CMDR.NACKMOD = 1, I2C module will automatically send NACK bit during acknowledge cycle and then enter ISR

    In Master RX mode:

    When I2CMDR.NACKMOD = 0, I2C module will automatically send ACK bit during acknowledge cycle until I2CCNT > 0 and send NACK bit when I2CCNT = 0.

    When I2CMDR.NACKMOD = 1, I2C module will automatically send NACK bit during acknowledge cycle irrespective of I2CCNT value.

    2) Can the I2C module get the 8-I2C-clock-cycle I2C data/command first and enter an ISR and make decision to send ACK or NACK later? That is, use SW-based ACK/NACK?

    No, you don't have a way to send ACK / NACK bit via SW method after entering ISR routine.

    Regards,

    Manoj