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TMS320F28379D: About SPI master mode

Part Number: TMS320F28379D

Hi 

I have a question about how to use  SPI master mode.

Attached file is the waveform of using SPI master mode.

I want to change SPISIMO positive edge timing.

Can SPISIMO’s positive edge timing change after the /SPITE negative edge?

Best regards

Naoki

  • Hello Naoki,

    This waveform doesn't look right, the SPISOMI should be toggling after the SPISTE pin goes low, not before. Can you clarify a few points:

    1. In your code is the SPISTE pin configured as GPIO or as SPISTE pin? Some customers configure the pin for GPIO mode and use the CPU set it low or high.

    2. On your board is there a pull-up resistor on the SPISOMI pin?

  • Hi 

    It was a question about SPISIMO pin. How about SPISIMO?

    Can SPISIMO’s positive edge timing change after the /SPITE negative edge?

    I will answer your answer below.

    I'm not using GPIO mode for SPISTE.

    There is a pull-up register on the SPISOMI pin. 

    Best regards

    Naoki

  • My apologies, I meant SPISIMO.

    Do you have a pull-up on SPISIMO?

  • Hi

    No, there is not pull-up on SPISIMO.

    I think it is a little strange waveform.

    Is there any setting that changes the timing of SPITE goes low?

    Best regards

    Naoki

  • I agree, it is strange. The SPISIMO pin should start toggling AFTER the SPISTE pin goes low, not before. This is not configurable. If you could post a snapshot of your schematic (SPI bus only) and SPI code, I can take a look.

  • SPISIMO is connecting directly to the slave device.

    BTW, I found 2 phenomenon of SPI waveform.

    1: After the communication is finished, SPISIMO signal goes high or low. Is this also strange?(Please see following picture)

    2: When I set CLKPOLARITY = 1 and CLOCK PHASE=0(SPI MODE3), SPISIMO start toggling timing after the SPISTE pin goes low.

       (Please see following picture)

        It seems this strange phenomenon is occur on SPI MODE0(CLKPOLARITY = 0 and CLOCK PHASE=1)

    Do these phenomenon help you understand the situation?

    Since SPITE can assign GPIO, I can easy to change SPITE timing.

    So I think It's not serious problem.

    If you can't think of a solution to settings, I'm going to end this post.

    Best regards

    Naoki

  • Naoki,

    I'm still not sure what could be happening here. What is the frequency of your SPICLK and also the internal LSPCLK and SYSCLKs?

    Does this behavior impact functionality of your system? Does the slave device receive incorrect data? If not, then I'd agree with you that this is not a serious problem.