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TMS320F280049C: SysCtl_setClock() gets stuck

Hitoshi Sugawara
Mastermind 20810 points

Part Number: TMS320F280049C
Other Parts Discussed in Thread: C2000WARE,

Hi Experts,

A customer has been facing the problem that SysCtl_setClock() gets stuck. C2000ware version is C2000Ware 2.01.00.00.
According to "3.7.10 System Clock Setup" in the TRM, it says that "3. Set up the system PLL if desired. TI recommends using the C2000Ware SysCtl:setClock() function for proper configuration of the PLL clock."
However, it has stuck at the loop in SysCtl_selectXTAL().

・CLKSRCCTL1.OSCCLKSRCSEL = XTAL
・SYSPLLMULT    12.5 times
・SYSPLLCTL1.PLLEN = SYSPLL enable
・SYSCLKDIVSEL.PLLSYSCLKDIV = /1

Could you please let us know how to utilize SysCtl_setClock() function.

Best regards,
Hitoshi Sugawara

  • 0
    TI__Mastermind 20810 points

    Part Number: TMS320F280049C

    Hi Experts,

    It seems that SysCtl_setClock() does not support the ODIV field in SYSPLLMULT register.
    Can ODIV field in SysCtl_setClock() set other than 0?
    Please let us know how to configure ODIV filed.

    Best regards,
    Hitoshi

  • 0 in reply to Hitoshi Sugawara
    TI__Mastermind 19795 points

    Hi Hitoshi,

    I have merged your two threads as they share similar topics.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Guru* 95315 points

    Sugawara-san,         

    • Is this problem seen with the latest version of C2000WARE (3_04_00_00)?
    • Is this problem seen with standard hardware like the F280049C LaunchPad?
    • Is this problem seen every time or only randomly?
  • 0 in reply to Hareesh Janakiraman
    TI__Mastermind 32695 points

    Sugawara-san,

    This is a known issue in the F28004x driverlib and we plan to update the function for the next C2000ware release. The function does not take into account the ODIV value. It uses DCC to validate the PLL output against the reference clock. It assumes the divider value is 1 and hence the calculated clock ratios are wrong.

    As a workaround, please use the attached sysctl driver with the updated function. This shall be included in the next official C2000ware release.

    sysctl.zip

    Sample PLL configuration : 

    #define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_ODIV(1) | SYSCTL_PLL_ENABLE)
                                     
SysCtl_setClock(DEVICE_SETCLOCK_CFG);

  • 0 in reply to Veena Kamath
    TI__Mastermind 20810 points

    Hi Veena,

    Is this the reason why the SysCtl_setClock() gets stuck too?
    Please let me just clarify.

    Best regards,
    Hitoshi

  • 0 in reply to Hitoshi Sugawara
    TI__Mastermind 32695 points

    Is it getting stuck in the while(SysCtl_isMCDClockFailureDetected()) loop? Please send the code snippet where it is getting stuck

    Are you using a ControlCard/Launch or a custom board? Please check is the XTAL is running fine

    Regards,

    Veena

  • 0 in reply to Veena Kamath
    TI__Mastermind 20810 points

    Hi Veena,
    According to the customer, it has stuck at the loop in SysCtl_selectXTAL() when they configured as follows:

    ・CLKSRCCTL1.OSCCLKSRCSEL = XTAL
    ・SYSPLLMULT    12.5 times
    ・SYSPLLCTL1.PLLEN = SYSPLL enable
    ・SYSCLKDIVSEL.PLLSYSCLKDIV = /1

    They would like to know the correct setting. 
    Best regards,
    Hitoshi Sugawara

  • +1 in reply to Hitoshi Sugawara
    TI__Mastermind 32695 points

    Hi,

    What is the XTAL frequency they are using? You need to make sure the clock frequencies are within the range specified in the datasheet.

    Are you using the ODIV parameter? Assuming the XTAL is 20MHz and ODIV=1, the output PLL frequency is outside the allowed range.

    What is the desired sysclk frequency?

    Regards,

    Veena

  • 0 in reply to Veena Kamath
    TI__Mastermind 20810 points

    Hi Veena,

    It seems that current SysCtl_setClock() does not support ODIV filed so the customer can not configure the target PLL frequency.
    Let me work with them to make the correct setting accordingly.

    Thank you for you prompt support.
    Best regards,
    Hitoshi

  • 0 in reply to Hitoshi Sugawara
    TI__Mastermind 32695 points

    I have attached the updated driver that supports ODIV configuration as well. Please use that for configuring ODIV.

    Regards,

    Veena

  • 0 in reply to Veena Kamath
    TI__Mastermind 20810 points

    Hi Veena,

    Let me re-start discussion on this. According to the customer, they are using their own board and the SysCtl_setClock() in sysctl.zip still does not work correctly.
    They have to use C2000Ware 2.01.00.00.

    Here is the PLL configuration as follows:
    OSCLK = 16MHz, NF = 12.5 ( FMULT =2, IMLT = 12), f(VCO) = 200MHz, ODIV =1 ( divider /2)
    PLLRAWCLK = 100MHz, PLLSYSCLKDIV = 1, SYSCLK = 100MHz

    Could you please check the SysCtl_setClock() if it works correctly?

    Thank you for your kind support.
    Best regards,
    Hitoshi

     

  • +1 in reply to Hitoshi Sugawara
    TI__Mastermind 32695 points

    Hi Hitoshi,

    I do not have C2000ware 2.01 installed, hence I am using v3.04. I believe that should not make a difference. I using the sysctl files available in the .zip file.

    I am using a Launchpad and has a 20MHz XTAL. This is the configuration in device.h:

    #define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(12) |  \
                                     SYSCTL_FMULT_1_2 | SYSCTL_SYSDIV(1) |   \
                                     SYSCTL_ODIV(2) | SYSCTL_PLL_ENABLE)

#define DEVICE_SYSCLK_FREQ          (uint32_t)((DEVICE_OSCSRC_FREQ * 12.5F) / (2))
     

    I have added (uint32_t) typecast for the DEVICE_SYSCLK_FREQ since it involves float operations.

    I am able to see a 125MHz  ( = 20 * 12.5 / 2) PLL output.

    Can you provide some details on the error you are facing? If the above code does not match your setting, can you share these 2 macro definitions?

    Regards,

    Veena

  • 0 in reply to Veena Kamath
    TI__Mastermind 20810 points

    Hi Veena,

    The customer has confirmed that sysctl.zip works correctly. 
    Thank you for your quick support on this inquiry.
    Please update the SysCtl_setClock() for the next C2000were release.

    Best regards,
    Hitoshi