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Questions on pipeline protection

Mokan Kanna
Intellectual 580 points


I am trying to optimize the high frequency ISR's performance in our application and was working on assembly routines. Refer spru430e (page 4-13). Under "Protection Against Register Conflicts", it says "All reads from and writes to CPU registers occur in either the D2 phase or the E phase of an instruction". Based on that, we can loose 1 to 3 cycles (ie) upto 4 times slower throughput.  How do we know which instructions do it till only D2 which ones do till E? 

In "Example 4−2. Diagramming Pipeline Activity", Is there not a pipeline stalling between instruction I4 and I5 by register conflict caused by AL? I do not understand how that is depicted in the pipeline diagram.  I also do not understand the significance of B + + symbols there.

Clarify the number of wait cycles inserted between the two following instructions:

 SUB AL, loc16First

 MOV loc16Second, AL

If AL is involved AH in two adjacent instructions, is that also register conflict? Is AL, AH are considered separate entities or the same (in deciding register conflict), as SXM mode certainly has a bearing on them to act as conjoined twins. Clarify.

The pipeline section needs some addtional details. Where can we find more documentation on that? Any pointer to the relevant resources will be thankfully appreciated.

Sayee

  • 0
    TI__Guru* 92200 points

    Mokan Kanna said:
    I am trying to optimize the high frequency ISR's performance in our application and was working on assembly routines. Refer spru430e (page 4-13). Under "Protection Against Register Conflicts", it says "All reads from and writes to CPU registers occur in either the D2 phase or the E phase of an instruction". Based on that, we can loose 1 to 3 cycles (ie) upto 4 times slower throughput.  How do we know which instructions do it till only D2 which ones do till E?

    Sayee,

    It can be a bit tricky to spot register conflicts.  I have started a wiki page that describes in general which are D2 and which are E.  There are still some exceptions to the guidelines - in particular for PUSH/POP instructions but hopefully this will help:

    http://processors.wiki.ti.com/index.php/C28x_Pipeline_Conflicts

    Mokan Kanna said:

    Clarify the number of wait cycles inserted between the two following instructions:

     SUB AL, loc16First

     MOV loc16Second, AL

    These are single cycle, assuming no memory conflict. EXE modified registers (ACC(AH/AL), P(PH/PL), XT are operated on in EXE phase. When you store the value to memory,. the register is read in EXE phase and then moves to W phase. So no conflict there.

    Mokan Kanna said:
     I also do not understand the significance of B + + symbols there.

    The column in the document unfortunately wrapped around.  These are part of the instruction itself.   I will note this for correction.

    Mokan Kanna said:
    If AL is involved AH in two adjacent instructions, is that also register conflict? Is AL, AH are considered separate entities or the same (in deciding register conflict), as SXM mode certainly has a bearing on them to act as conjoined twins. Clarify.

    There is no conflict between AL and AH, they are treated as seperate registers.

    Regards,

    Lori